SU1396139A1 - Adder - Google Patents

Abstract

The invention relates to computing and can be used in the development of high-speed digital information processing devices. The purpose of the invention is to simplify the device by changing the bit conversion algorithm. cuts and converting compacted code to unitary code. The totalizer contains a permanent storage unit 1, the first and second groups of elements AND 2.3, the group of delay elements 4, and a binary code converter into compressed code 5. To achieve the purpose of the invention, a group of elements NO 6. is entered. 2 Il. I (L

Description

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The invention relates to computing technology and can be used in the development of high-speed digital information processing devices.

The purpose of the invention is to simplify the device.

The diagram shows the block diagram of the totalizer; Fig. 2 shows the placement of information in a permanent storage unit for the case of processing 5 operands.

The totalizer contains a permanent storage unit (PZB, 1 1 first and second groups of elements AND 2 and 3, a group of elements of delay A, a binary code converter 5 and a compressed code (PD7), a group of elements NOT 6, and the first steps of the first group of elements And 2 are connected to the synchronization input 7 of the device, the inputs of the remote control 5 are connected to the outputs of the corresponding elements 4 delays and the outputs from the nth to the 2nd - with the second inputs of the corresponding elements And 3 of the second group, the information inputs 8 of the device are connected to the second inputs of the corresponding x elements AND 2 of the first group, the inputs of the group of elements NOT 6 are connected to the corresponding outputs of the remote control 5, and zykhods, except for the n-th element NOT b, are connected to the first inputs of the elements And 3 of the second group, the address inputs of the PZB 1 are connected respectively with the output of the nth element NOT 6, the outputs of the elements I 3 of the second group and the first output of the ODU 5, the first bit output of the PZB 1 is connected to the output 9 of the device, and the remaining bits are connected to the inputs of the corresponding - STV lean elements 4 delays.

The device works as follows:

The inputs 8 receive the same-named bits of all the terms starting with the lower bits, which through the elements AND 2 arrive at the inputs of the remote control 5 during the clock pulse through the input 7. The second part of the inputs of the remote control 5 connected to the outputs of the delay elements 4 receives the sign of transfer formed in the preceding summation cycle. At the output of the remote control unit 5, a compressed code is formed corresponding to the number of logical units in the code that was assigned to its input.

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The unit, which includes a group of elements HE 6, And 3 elements and a connection from the first output of the remote control 5, is intended to form a unitary code from the compressed code. The generated unitary code activates one of the lines of the TZB 1, as a result of this, the discharge of the result at output 9 and the signs of transfer to the next summation cycle, which arrive at the delay elements 4, are read. Total number of ticks of the sum calculation

m p, N, where n is the resolution of the components; N is the number of terms.

Let it be necessary to sum up the following five terms: 101101, 1 10110, 011101, 110111, 100101.

The processed sections at the output of the And 2 elements are: 10111,01010 11111, 10100, 01110, 11011.

During the first clock pulse applied to the synchronization input 7, the bit slice of the lower bits of the lOil components and the transfer flag 0000 are supplied to the input of the remote control 5, since the first line of the OTL 1 was activated in the initial state. At the output of the remote control 5, a code 000001 111 is formed, and after converting it to a unitary code, the code 000001000 is obtained. The received unitary code activates the fourth line of the OTL 1, while the output 9 of the result receives the value o, and the transfer attribute is equal to OOP o

The value of the delay time of the signal generated by the element 4 delay,

equals:

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where T (. is the arrival period of the sync pulsations;

T. 5 - Delay of signals on the remote control 5, PZB 1 and the block for converting compressed code to unitary,

By the time the remote control unit 5 arrives at the second bit slice, which is fed at the time of the second clock pulse and equal to OJOIO, the second part of its inputs will receive a sign of the transfer of the OOP. At the output of the remote control 5, an LLCOOP code will be generated, and after conversion to unitary, 000001000. In the IZZ 1, the fourth line will be activated.

the value, the result is O, and the sign of the transfer - OOP

In the third cycle of the device operation, the code 111110011 is received at the input of the remote control 5. After the conversion, we obtain the compressed code 001111111, and the corresponding unitary code is 001000000. The result value 1 and the sign of transfer equal to 0111 will be read at this address from

Similarly, the proposed device continues to work until the eighth digit amount. The result is equal to 11011100. In the seventh and eighth cycles, zero codes arrive at the input of the And 2 elements.

Claims (1)

Invention Formula A totalizer containing a permanent storage unit, the first and second groups of elements AND, a group of delay elements, a binary code converter into a compressed code, the first inputs of the AND elements of the first group are connected to the synchronization input of the device, the inputs of the first binary code converter group in the compressed code are connected to the outputs of the corresponding delay elements of the group, the outputs of the binary code converter in the compressed code from the nth to the second (where n 2t-1; m is the number of operands) are connected to the first in With the signals of the corresponding elements AND of the second group with (nl) -ro through the first and second, so that, in order to simplify the device, the group of elements NOT is entered into it, and the information inputs of the device are connected With the Second the inputs of the corresponding elements of the first group, the inputs of the elements of the NOT group are connected to the corresponding outputs of the binary code converter into the compressed code, the outputs of the elements of the NOT group, except for the n-th, are connected to the second inputs of the corresponding elements of the second group, the address inputs of the permanent storage unit The output is connected respectively to the output of the nth element of the NOT group, the outputs of the elements of the second group and the first output of the binary code pre-n into the compressed code, the first bit output of the permanent storage unit is connected to the output of the device, and the remaining bit outputs are connected to the inputs of the corresponding delay elements of the group, the outputs of the elements And the first group are connected respectively to the inputs of the second group of the converter of the binary code into the compressed code. s in 6 in 7 Fi & .2