SU1478219A1 - Multiinput signature analyser - Google Patents

Abstract

The invention relates to computing and can be used in systems for monitoring and diagnosing digital devices. The aim of the invention is to increase speed. The analyzer contains high-frequency inputs 1, clock input 2, outputs 3 registers, groups of N multiplication blocks 4 modulo L, addition blocks 5 modulo L, designed to combine the input data sequence with the current signature value, to blocks 6 division modulo L, N registers 7 for storing signatures, orthogonal memory blocks 8, to groups 9 parallel outputs of an orthogonal memory block, clock divider 10 for obtaining the internal clock frequency of the analyzer. Block 8 of the orthogonal memory contains shift registers for converting the input binary sequence from a serial code to a parallel code and buffer registers. 1 hp f-ly, 2 ill.

Description

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The invention relates to computing and can be used in systems for monitoring and diagnosing digital devices.

The aim of the invention is to increase speed.

Figure 1 shows the structural diagram of the analyzer; Fig. 2 shows the functional scheme of the orthogonal memory block.

M-input t-type analyzer (Fig. 1) contains a group of information inputs 1, a clock input 2, a group of information outputs 3, K groups of N blocks 4 multiplying modulo L. K blocks 5 adding modulo L, K blocks 6 dividing modulo L , N registers 7, block 8 orthogonal memory, K groups 9 parallel outputs of the orthogonal memory block, divider 10 clock frequency. In this case, K is the input information width; N is the degree of the primitive polynomial over the field GF (L), a,) is a prime number.

Block 8 of the orthogonal memory (FIG. 2) contains K shift registers 11 and K buffer registers 12.

The analyzer works as follows.

Before starting, all registers are set to the state 0 ... 0. The circuit for setting the registers to the initial state is not shown. Let high-frequency binary sequences arrive at high-frequency inputs 1

A, “, () ci, (2) ... o6, (n);

A2 (D 44 (2) ... oi4 (ft); A 0 (1) 0 (2) ... oi-K (n),

where K is the number of input lines, R, n is the division factor of the counter 10.

After the arrival of the nth high-frequency clock pulse, a pulse will be formed at the output of the divider by n (10), and in the registers 12 of the orthogonal memory there will be a code that noj would appear in the analyzer having K groups by n-inputs.

A „about1, (1); etI4 (l); And, to cilk (l)

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Or change the indices I 1, K for a high-frequency sequence of length m x n, we write

Hell, et Ll (l) o611 (2) ... ctll (m); (1) L 12 (2) ... еЫ2 (t);

A „oiln (l) can (2). .. oiln (m)

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Thus, after the arrival of p jf m-ro pulse, the analyzer registers will have a code that uniquely corresponds to the remainder of modulo 1 division of the input sequence polynomial.

A et, l (1Y1 (1) ... LC (1) e61 (2) (2) ... ... w / c (2) ...

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on a polynomial inverse with respect to the primitive polynomial F (x).

In this case, summation, division, multiplication and memorization is carried out with a clock frequency.

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high frequency inputs. Compared to the known, the proposed analyzer has the ability to process high-frequency data input sequences, as well as increased noise immunity and low power consumption due to the possibility of using low-frequency chips with high clock frequency and high power consumption and low power consumption, such as CMOS, for processing high-frequency sequences. .

Claims (2)

Invention Formula I. Multi-signature signature analyzer, containing N registers, where N is the degree of a primitive polynomial over the field GF (L), a L6 (2tl, 2) is a prime number, K addition blocks modulo L, where K is the input information width, K blocks modulo L, K groups of N multiplication units modulo N, and the inputs of the 3rd addition block modulo L (, K) are connected to the inputs of the i-ro division module modulo L, the outputs of which are connected to information inputs (K- The i + I) -th register and with the inputs of the j-gr multiplication unit modulo L, j, i (K + ji) -ft groups, the outputs of the 1st register, 1, N, are connected to the input s of the m-th multiplication unit modulo L,, N-1 + 1, the t-th group, the group of information inputs of the P-th register,, N, is connected to the output group of the (Р-К) -th register, the group of outputs of the blocks cleverly - module modulo L of the i-th group are connected to the corresponding groups of inputs of the 1st addition unit modulo-two, characterized in that, in order to improve speed, the analyzer contains an orthogonal memory block and a clock frequency depot, and a group of information inputs block orthogonal 0 S 0 5 the memory is the corresponding stgpukgdey group of inputs of the analyzer, the 1st group of information outputs of the orthogonal memory block is connected to the (K + 1) -th group of inputs of the 1st modulo-L adder, the input of the clock divider is connected to the first one-1 the input of the orthogonal memory block and forms the clock input of the analyzer, the output of the clock frequency divider is connected to the second clock input of the orthogonal memory block to the synchronous inputs of registers, 2. The analyzer of claim 1, about tl, is that the orthogonal memory block contains K buffer registers and K shift registers, the information inputs of which form a group of information inputs of the block, the shift control inputs connected to the first clock input of the block, outputs 1 The th shift register is connected, respectively, with the information inputs of the i-ro buffer register, the outputs of which form the i-th group of information outputs of the block, and the synchronization of the buffer registers are connected to the second clock input of the block. FIG. 2