SU1256162A1 - M-sequence generator - Google Patents

Abstract

This invention relates to pulsed technology. The purpose of the invention is to expand the functionality of the device. The generator contains a generator of 1 pulses, N registers 2, element OR-NOT 6, blocks 3, 4 and 5 of addition, division and multiplication. Introduction of (kl) -blocks 3 add, (kl) division blocks 4, (kl) of multiplication blocks 5, element 7 and bus 8 Control with the formation of new connections between the elements of the device, increases the period of the generated sequence and the magnitude of the sequence shift by neighboring registers. 4 il. § (L

Description

The invention relates to a pulse technique.

The purpose of the invention is to expand the functionality by increasing the period of the generated sequence and the magnitude of the shift of sequences on neighboring registers.

FIG. 1 shows the structure of an M-sequence generator for N-3; FIG. 2 is the same in FIG. 3 - the same for N 1, in FIG. 4 - the same, dl,.

The M-sequence generator contains a generator of 1 pulses, N registers 2, k blocks of 3 additions, k blocks of 4 divisions, k groups 5 of n blocks of multiplication, the element OR NOT 6, the element AND 7, the bus 8 Control connected to the first input of the element And 7, the output of which is connected to the corresponding inputs of the second group of inputs of the first block 3 of addition.

to

15

20

outlets (N-1) - of which, and all, out, the outputs are connected by the element OR-NOT 6.

Registers 2 have a bit of day. Blocks 5 are multiplied, 3 is a division of divisions carried out with real corresponding operations in

The unused groups of the first block 3 add-on with with the power bus (total

FIG. Figure 2 shows an example of the structure of a device for arithmetic of a polynomial (x) and N. In this case, the composition of each 5 multipliers of the input block (coefficients, different zero, forming a polynomial). One of them carried out knitting on I, i.e. transmits from input to output without changing FIG. 2 not shown). In this case, blocks 4 form a polynomial division by 1 (not Since, i.e.,

,, - J --- J-, - -,.,

The corresponding outputs of the blocks of multipliers between registers 2 are not.

Neither the 1st group 5 of the p multiplication units (, k) are connected to the inputs of the corresponding i-ro block 3 whose outputs are connected to the inputs of the corresponding i-ro block 4 division. The outputs ix of registers 2 (il, Nk) are connected () to the information inputs (i + k) -x of registers 2. Information inputs ix of registers 2 (i, min (k, N) are connected to the outputs of the corresponding dividing units 4. Outputs the corresponding jx registers 2 (j N-i + l) and kx dividing blocks 4 () are connected to the inputs of the multiplication blocks of the i-th group 5 of n blocks of mental multiplicity. The input groups of the i-th block 3 of addition (i (N + l ), k) through the corresponding multiplication blocks of the i-th group 5 of the n multiplication blocks are connected (when) with the outputs of the corresponding jx division blocks 4 (). The second input of the And 7 element is connected to the output of the element This OR is NOT 6. The outputs N of registers 2 are connected to the corresponding inputs of the multiplication units of the first group 5 of h multiplication units, the outputs of which are connected to the first group of inputs of the first addition unit 3, the outputs of which are connected to the inputs of the first division unit 4. Generator output 1 - pulses connected to the synchronization inputs of N registers 2, the outputs of the

outlets (N-1) —which and all but one of the outputs are connected to the inputs of the element OR — NOT 6.

Registers 2 are of the size p. Blocks 5 multiplication, 3 additions, and 4 divisions are carried out with the implementation of the corresponding operations in the field of CES (2).

The unused input groups of the first addition unit 3 are connected to the power bus (common bus).

FIG. 2 shows an example of constructing a device for forming a polynomial (F) and,. In this case, the structure of each group of 5 multiplication blocks includes two blocks (coefficients other than zero, which form a two-dimensional polynomial, i.e.). One of them multiplies by I, i.e. transmits signals from input to output without changing (not shown in Fig. 2). In this case, the dividing units 4 in this forming polynomial are divided by 1 (not shown). Since, i.e. , then sv - J --- J-, - -,.,

When building a device for and (Fig. 3), the outputs of each i-ro register 2 are connected to the inputs (i + 1) -ro of the register, where, N-1. At the same time, for example, the outputs of each i-ro register 2 (, N-k) are connected to the inputs (i + k) -x of registers 2, etc. FIG. 4 is an example for T (x),,.

The device works as follows.

The operation of the M-sequence generator occurs in two modes: when - on the bus 8 The control is a high level signal and when on the bus 8 the control is a singal of the low level.

In the second mode, before starting work in one of the registers 2, a non-zero code must be written (installation circuits are not shown). Logical O on bus 8 The control blocks the flow of signals to the second group of inputs of the first block 3 of addition. In this situation, when the generator operates in the usual way in accordance with the matrix

31256

where Ы.С GF (2) are the coefficients of the formation of a small polynomial F (x) o (x + ... o (+ ....

For the device shown in FIG. 4, this matrix has the form:

T

uJ

If) and q (j + l) are the contents of the j-ro register 2, respectively, before and after the arrival of the j-ro pulse from the pulse generator 1, then we can write

q (j + l) lq, (j) uJq (j) q (.l + l) bq, (j) + 0-q (j)

T

q / j)

q, (j)

The period of the M-sequence with logical O on bus 8 Control is equal to (2 -1).

Consider the operation of the generator in the first of these modes. Let registers 2 be in the state О О ... О oi, where the element of the Galu field oL is determined by the output number of the first register 2, which is not connected to the inputs of the OR-NOT 6 element. For the devices shown in FIG. 2 and 4, oi. 1, since the first bit of the second register 2 is not connected to the inputs of the OR-NOT 6 element. If we connect the first and not the second bits of the second register to 2.0 uJ to the input of the IPI element NE 6 (this element corresponds to in the register code 10). At the output of the element OR-NOT 6, a signal of logical 1 appears, since all its inputs have zeros. On mime 8, the control in this mode is also logical 1,

Thus, the corresponding inputs of the first block 3 add

Logical 1 is received from the output of element 7. The inputs of the second group of the first block of 3 addition, to which the output of element 7 is connected, are chosen so that this group of inputs contains a code corresponding to the element of the GF (2) field (), where ot. - coefficient of the higher term of the generating polynomial. For the devices shown in FIG. 2 and 4, (IZ (on the second

1256

-

a 5

e 10

0 i)

15

20

,,. °

Jq 55

1624

the input group of the first block 3 add code 1 nj.

At the moment of the arrival of the next pulse from the output of the pulse generator 1, the zero code in the first group of inputs of the first addition unit 3 (Fig. 2 and A), the code in the second and third groups, i.e. at the outputs of the first block 3 of addition, the zero code and - after the arrival of the pulse, all registers 2 are in the state O ... O, which is rare (which increases the succession period). At the output of element 6, the potential is still high, i.e. on the second group of inputs of the first block 3, the code is still kodo (. After the next pulse arrives from the pulse generator 1, the registers 2 are in the state J / O ... 00. Then the device continues in the usual way.

When k 1 in the device, in one clock cycle, the code defined by the matrix describing the operation of the M-sequence generator at k 1 and having the form T, which allows increasing the shift between the M-sequences taken from the outputs of the neighboring registers 2.

Claims (1)

Invention Formula An M-sequence generator containing N registers, the outputs of which are connected to the corresponding inputs of the multiplication units of the first group of n multiplication units, the outputs of which are connected to the first group of inputs of the first addition unit, the outputs of which are connected to the inputs of the first division unit, the pulse generator E whose output is connected with synchronization inputs of N registers, the outputs of the first (N-1) which and. all but one of the outputs of the nth are connected to the inputs of the OR-NOT element, characterized in that, in order to extend the functionality by increasing the period of the generated sequence and the magnitude of the sequence shift on neighboring registers, it contains (k-l) addition blocks, (k-1) division blocks, (k-l) groups of n multiplication blocks, And element, bus Control connected to the first input of And element whose output is connected S12561 with the corresponding inputs of the second group of inputs of the first addition block, the corresponding outputs of the multiplication blocks of the i-th group of the multiplication blocks n (k) are connected to the inputs 5 of the corresponding i-ro addition block, the outputs of which are connected to the inputs of the corresponding i-ro division block , the outputs of the ix registers (, Nk) are connected (when), c, with the information inputs (i + k) -x registers, the information inputs of the ix registers, MMH (k, N) J are connected to the outputs 62-in the corresponding division blocks, the outputs of the corresponding registers (li N-i + l) and kx division blocks (l kti-1) are connected to the inputs of the multiplication blocks of the i-th group of n multiplication blocks, the input groups of the i-ro addition block i (N + l), k are connected to the outputs of the corresponding jx division blocks () through the corresponding multiplication blocks of the i-th group of multiplication blocks (), the second input of the AND element is connected to the output of the OR-NOT element. phases FIG. Editor V. Petrash With aviJ spruce U. Burmistrov Tehred M.Hodanich Order 4834/55 Circulation 816. Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader I. Muska