SU1354416A1 - Frequency divider with variable division number - Google Patents

Abstract

The invention relates to a pulse technique, can be used in automation and computing devices, in frequency synthesizers and provides an increase in speed. The proposed frequency divider contains a high frequency divider 1 frequency ,, input bus 2, program-. dividing dividers 3 and 4 frequencies, triggers 5 and 6, elements AND 7 and 8, element OR 9, control unit 10, code lines 11, 12. Frequency divider 1 contains D-triggers 13.1-13.P, element OR 14, element And 15, 1K-flip-flop 16. In the proposed frequency divider, the variable division factor K can be equal to 26. 2z.p. ff, 1 ill. (L with do eat

Description

 13544162

The invention relates to a pulse -..., 13- (p-1), 13-p, inverse output technique and the last of which can be used is connected to nep-i in automation devices and the computer input of the element OR 14, the output boiler room equipment, in synthesizers, for example, is connected to the first input. And 15, the second input of which is the purpose of the invention - the increase would be dinin with the inverse output of the first

Strodeystvii .D- -trigger -13-1, output - with the information on the drawing shows the electrical input of this trigger; clock

: ka functional diagram of the device. JQ inputs of the first and nth D-flip-flops 13-1

The frequency divider with variable ko and 13-n is connected to the clock input by the dividing efficiency contains a high-high frequency divider 1 frequency, frequency divider 1 frequency, clock-inverse outputs of D-flip-flops 13-2, the left input of which is connected to the input 13- (p- 1) from the second to (p-1) -th connection of 2, the first output - with clock. 15 yens with their information input, and the inputs of the first and second program-inverse output (nl) -ro D-triggered dividers 3 and 4 frequencies, c13- (p-1) are connected to the clock input by clock inputs of the first and second 1K-trigger 16 and to the first output in Triggers 5 and 6 and with the first inputs of the frequency splitter 1 frequency, the first and second elements And 7 and 8; 20 whose second output is connected to the output (direct) resolution of the first pass of the 1K-flip-flop 16 and the second input of the 3 frequency divider by the element ID OR 14, the third input is connected to the second (inverse) of the second programmer output (n-1) of the splitter 4 frequency is connected to the D-flip-flop 13- (p-1) and to the second output of the high-frequency de-25 th input of the n-th D-flip-flop 13-n, frequency 1; the outputs of the first and the first, second and third controlling third programmable dividers 3 inputs high-frequency divider 1 and 4 frequencies are connected to the information. the frequencies are connected to the corresponding inputs of the first I, K, and S inputs of the G flip-flop 16, respectively; and second triggers 5 and 6 and the corresponding clock inputs of the triggers from the second with the first and second control-by (n-1) -th are connected to the direct outputs of the high-frequency dividers of the previous triggers. The frequency unit 10 1, the third control input control unit contains an inverter unit 17 which is connected to the elementary output and the first and second adders 18 OR 9 with output inversion (elements 19, the outputs of which are connected respectively OR), the inputs of which are connected the first and the second group - the first group of inputs (the lower part of the outputs of the control unit 10, the row inputs) of the control unit 10 and from the first first operand of the first adder to the code bus 11; the second code bus 18 is connected to the bus of the unit level 12 connected to the second group of inputs, the inputs of the second operand to the first (senior bits) of the unit 10 by the control group of the inputs of the control unit 10; through the block 17 inverters with inputs of control block 10 are connected to the first operand of the second adder by the formation inputs, respectively, the inputs of the second operand of the first and second programmable are connected to the second group of dividers inputs 3 and 4 frequencies, the input of the pre-control unit 10 . The literal installation (recording) of the first device works as follows, the upholstery of which is connected to the reset input.

the first trigger 5 and with the output of the first division factor of the separator of the clock element I 7, the second input of which is with a variable del-ratio connected to the output of the first trigger of the PDKD is 5, the second input of the element 8 of the connector N (L-Mj + (N + 1J M, with the course of the second flip-flop 6, the input N is the division ratio of which is reset to output 1;

the second element And 8 and with the entrance of the pre-m - the code value on the bus 11;

The second install (write) is the second; L is the code value on bus 12; go programmable divider 4 frequency. moreover (N (and, where n High-frequency divider 1, frequency, number of D-flip-flops 13-1, 13-213, contains n-D-flip-flops 13-1, 13-2, - (n-1), 13-n in divider 1.

313

The values of the setting codes on buses 11 and 12 can be determined from the expressions, respectively, 1,2,.,., (); , (N + U, (N + +2;, ..., (2 -U,

where m and & are the number of tire bits 1 1 to 12, respectively, with and t t. Based on the above ratios, the minimum and maximum values are

dividing coefficients DP K K - f7 "

- to 9 in. 1 max.

.

dpcd

(2 "-1) +

The division factor of divider 1 is determined from the condition of lowering the input frequency to the operating frequency, dividers 3 and 4. Then we take, and, we also take

We will consider the work of DPCD for cases and.

With the DPKD setup code, it has the view 010000. The last two bits of the code (on bus 11) define the code of the lower bits of the PDKD. Since its value 00 is equal to zero, element 9 sets trigger 16 to one state, which enables operation of divider 4, prohibits operation of divider 3, and through element 14 allows the resolution to element 15. In this case, the division factor of divider 1 is equal to 4. The remaining The bits of the DPKD installation code determine (on bus 12) the code of the higher bits 0100. This code goes to the adder 19. To the other input of this adder, the code 17 is inverted by the mpadgap code. The adder 18 performs the operation of adding the codes 0100 and 1111 ,. the result of which 0011 arrives at the information inputs of the divider 4, which counts the pulses coming from the first output of divide 1. After the third pulse at the output of divider 4, it resolves to the K-input IK-. the trigger 16 and the information input of the trigger 6. The next pulse trigger 6 switches to the opposite state, after which the inputs of element 8 are in two permitting levels, and at the output of element 8 there is a voltage drop, which sets divider 4 and trigger 6 the initial state, after which the PDCD cycle will be repeated. Thus, the division ratio of the DPCD is equal to.

Q

five

five

0

5 o Q

five

sixteen

With the installation DCDD code looks like 011010. The last two digits of the code, equal to 10, are sent to Adder 18, to the other input of which is received code 11. The result of summation in adder 18, equal to 01, is fed to informational inputs of divider 3. The result of summation in adder 19 from codes 0110 and 1101, the same 0011 enters the information inputs of divider 4. We assume that the 1K flip-flop 16 is in the zero state, then divider 4 is allowed, divider 4 is forbidden, divider 1 divides the input frequency by 5. From the first impulse arriving at the input d divider 3, at its output is :: Wits the enabling level, which is fed to the 1 input of the 1K flip-flop 16 and to the information input of the flip-flop 5. Triggers 16 and 5 switch from the second pulse, while at the input of the element 7 the Wits allow the level, and at its output a difference, setting the divisor 3 and the trigger 5 to the initial state. After that, the divisor 1 will begin to divide by 4, starts. divider 4 is working. After the third pulse arriving at the input of divider 4 (the fifth from the start of counting), at its output, the resolution level is fed to the K-input of the Z-flip-flop 16 and to the information input of the flip-flop 6. From the next pulse triggers 16 and 6, while at the output of element 8 there is a differential, setting divider 4 and trigger 6 to the initial state, divider 4 is simultaneously disabled, divider 3 is allowed, and divider 1 switches to division factor 5. Then the cycle KDPD repeats . Thus, the division ratio of DPCD is equal to

Claims (1)

Invention Formula 1. A frequency divider with a variable division factor, containing a high-frequency frequency divider, the clock input is connected to the input bus, and the first output is clocked at the inputs of the first and second programmable frequency dividers, the control unit, the first element, And, the element OR, whose inputs are connected to a first code bus, and a second code bus, characterized in that. that, in order to improve speed. BHHj two triggers and the second element AND are entered into it, and the OR element is executed with inversion at the output, the first inputs of the first and second elements AND are connected to the clock inputs of the first and second triggers and the first output of the high-frequency frequency divider, the second output of which is connected to the resolution inputs of the first and second programmable frequency dividers, the outputs of which are connected to the information inputs of the first and second flip-flops respectively and with the first and second control inputs of the high-frequency de frequency frequency, the third control input of which is connected to the output of the OR element, whose inputs are connected to the first group of inputs of the control unit, the second group of inputs of which is connected to the second code bus, the first and second groups of outputs to the information inputs of the first and second programmable frequency dividers, respectively , the pre-installation input of the first of which is connected to the reset input of the first trigger and with the output of the first element I, the second descent of which is connected to the output of the first trigger, input the input Fitting noy second programmable frequency divider coupled to an output of the second member ten D-flip-flop, the clock input of which is connected to the clock input of the high-frequency frequency divider and the clock input of the first D-flip-flop whose information input is connected to the output of the AND element, the first input of which is connected to the output of the OR element, the second input to the inverse output of the first D-flip-flop, clock input of each of the D-flip-flops from the second to (n-1) -th are connected to the direct outputs of the previous D-flip-flop, the information input of each of them is inverse 15 of its own D-flip-flop, the inverse output of the (n-1) -th D-flip-flop is connected to the clock input of the 1K-flip-flop using the first output of the high-frequency frequency divider, the second output of which is connected to the output of the 1K-flip-flop and the second input of the element OR, the third input of which is connected to the direct output of (nl) -ro D-flip-flop and to the information input of the n-th D-flip-flop, the first, second, and third control inputs of the high-frequency frequency divider are connected to I, K, and S-inputs 1K-trigger. 20 thirty 3. The frequency divider according to claim 1, characterized in that the control unit contains a block of inverters and two adders, the inputs of the first operand of the first of which are connected to the bus of a single level, the outputs - with And with the reset input of the second trigger, the first group of outputs of the control output block of which is connected to the second input of the second element I, 2 in the frequency divider according to claim 1, about t - l and h a to u and with the fact that the high-frequency frequency divider contains n B-flip-flops, W-flip-flop, the AND element and the OR element, the first input of which is connected to inverse nth output Compiled by A.Sokolov Editor L.Gratillo Tehred M.Hodanich Order 5714/55 Circulation 900. . Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 ten 544166 D-flip-flop, the clock input of which is connected to the clock input of the high-frequency frequency divider and the clock input of the first D-flip-flop whose information input is connected to the output of the AND element, the first input of which is connected to the output of the OR element, the second input to the inverse output of the first D-flip-flop, clock input of each of the D-flip-flops from the second to (n-1) -th are connected to the direct outputs of the previous D-flip-flop, the information input of each of them is inverse 15 of its own D-flip-flop, the inverse output of the (n-1) -th D-flip-flop is connected to the clock input of the 1K-flip-flop using the first output of the high-frequency frequency divider, the second output of which is connected to the output of the 1K-flip-flop and the second input of the element OR, the third input of which is connected to the direct output of (nl) -ro D-flip-flop and to the information input of the n-th D-flip-flop, the first, second, and third control inputs of the high-frequency frequency divider are connected to I, K, and S-inputs 1K-trigger. 20 thirty 3. The frequency divider according to claim 1, characterized in that the control unit contains a block of inverters and two adders, the inputs of the first operand of the first of which are connected to the bus of a single level, the outputs - with No, the inputs of the second operand are with the first group of inputs of the control unit and through the block of inverters with the inputs of the first operand of the second adder, the outputs are connected to the second group of outputs of the control unit, the inputs of the second operand are connected to the second group of inputs of the control unit. Proofreader G. Reshetnik