SU1665382A1 - Device for mathematic functions computation - Google Patents

Abstract

The invention relates to computing, in particular, to methods and devices for processing mathematical functions. The purpose of the invention is to increase speed. The goal is achieved in that the device contains a control block 1, a data distribution block 2, a simple operand extraction block 3, a simple operand distribution block 4, K calculation blocks 5, where K is the level of a complex operator, and (K - 1) AND 6 2 il.

Description

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The invention relates to computing, in particular, to methods and devices for processing mathematical functions.

The purpose of the invention is to increase speed.

Figure 1 presents the scheme of the device; Fig. 2 shows an example implementation of the calculation block.

The device contains a control block 1, a data distribution block 2, a simple operand extraction block 3, a simple operand distribution block 4, calculation blocks 5, where k is the level of a complex operator, and (k-1) AND 6 elements. Each of calculation blocks 5 contains the first register 7, node 8, calculating the sum of units, the second register 9, the switch 10 and the node 11 synchronization.

The device performs positional equivalent transformations of the input signals and calculates the values of the positional operators from these input signals for any logic algebra (PLL) function. Positional equivalent transformations are performed by interchanging the input signals according to the formula

V q (X), where X is the vector of input signals;

Y is the vector of input signals, rearranged according to q;

q is a positional equivalent transformation.

Positional operator is determined on the basis of Si S (Y), n

where Yj is the sum of the units of the set Y;

S (So, Si Sn) - set, specifying

positional operator, and the length of the set S is one more than the length of the set X.

The positional operator is represented as follows: $ jk, where K is the dimension of the set to which the operator is applied.

 2 S ..

I o

To extend the class of representable functions, a complex positional operator is introduced.

... sЈ sJV sf0 °,

which we also take to the input set, but its property is that Sf ° is applied to the first K0 coordinates of the set Y, for SJVnepBOu the coordinate will be Wo, the result of the application, and the next Ki coordinates is Uko + 1Uko.

For the formal definition of a p-ary positional operation, we will consider a binary set of length n, denoted by X, i.e. X (Xi, X2, ..., Xn). Positional

the operation on this set is defined as follows: the n-ary positional operation is given by a binary set of length n + 1, i.e. S (SoSn). Each element of the set S corresponds to a specific position in

0, the set X is such that the element So is preceded by Xi, the element Si is between Xi and Xn-1, and the element Sn follows the element Xn. The presence of an operation in the f-th position means that, and the absence of - Si - 0.

5 A defined n-ary positional operation specifies an action on the arguments. To distinguish the action itself, the concept of a simple positional operator is introduced. A set of operations is called a simple positional operator. The number of characters of this operator must be one greater than the number of characters in the set to which this operator applies. The effect of the operator S on the set is determined as follows: if the operator S in the position i (I Ј 0 ,,. П) is one, then the result of applying the operator S to the set X will be equal to one in that, and only when set X contains I units.

0 To write simple positional operators, we will use the following notation:

Sjk

where K is the uniformity of the set X, to which 5 the operator is applied

-Ј 21 Si.

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With the help of simple operators, we can represent only symmetric PAL. In order to extend the class of functions represented by positional operators, a complex positional operator is introduced.

5S-SJfr ... SJV Sfr,

which is also applicable to the set X, but its property is that sjo ° is applied to the first K0 coordinates of the set X, for XJV the first coordinate is Y0 - the result of applying SJo °, and the next Kch coordinates is Xk0 +1. XK0 + 2 XKO + KI

Similarly, for sЈ, the first coordinate will be UT - the result of applying 0 SJV Sf0 °, and the following "2 coordinates are

HK0 4- K +1, HK, HK O + K1 + 2 XK0 + K1 + K2

and so on. The dimension of the set X is associated with a complex operator as follows:

n Ko + Ki + K2 + ... + K.

With the help of a complex positional operator, it is possible to represent at least one PLL of any preassigned level (we understand by the sublevel the number of ones in the set of function values). To obtain from a single function with a given number of arguments and a level any function with the same number of arguments and the same level, it is necessary to use positional equivalent transformations. Each particular transformation is defined by the code of this transformation. With the help of the positional operator and the transformation, we can represent any FAL as follows: f (x) S (q (x)) z, ze (0,1), where S is the positional operator;

q - conversion from the full estimate of equivalent converters.

If we use the same alphabet to represent operators and data, then we can perform not only operators and transformations on data, but also operators and transformations on operators and transformations. For example, let's calculate the values of the formula (Htf X2) V (Xi and X2) using the operator approach.

In the operator approach, we translate the formula (X2) V (X1L X2) into an operator view — this will be (0 (010) 1 (001) 1), and we perform operator 011 on operators 010 and 001 — this will be

010 001

Computed the resultant operator, we use the rule given in its definition, i.e. we find the sum of zero bits of the operators 010 and 001, it is 0, zero is in the 011 operator, which means that there will be zero in the zero-position in the resulting operator. Next, we find the sum of the first bits, it is equal to one, and in operator 011 there is one in the first position, which means that the unit will be in the first position of the resulting operator. The third bit of the resultant is calculated similarly to the second. In fact, we will perform a convolution of the formula to one operator 11, which has the same truth table as the original formula.

The device works as follows.

The information input of data distribution unit 2 is supplied with an input data set, the number of arguments of a simple operator from a selection unit 3 of simple ones is supplied to its second control input.

15 operators, and the first control input is the number of the operator from block 1 of the control. A complex positional operator arrives at the information input of the block 3 for selecting simple operators.

0 of the simple positional operator of block 3, the simple information position of the operator arrives at the second information input of the operator distribution block 4, and the output of the number of simple operator arguments is the number of arguments used in this simple operator, which is fed into the data distribution block 2.

On the leading edge of the starting pulse, a multi-phase generator is started.

0 in block 1 of the control, which generates a series of four pulses t, T2, T3, TA. as well as a single clock signal G0 frequency fn. Simultaneously with the filing of the starting pulse in the control unit 1 in blocks 2 and 3

5, corresponding input signals are provided that are strobed by a clock t0. Simultaneously with the clock pulse, the control unit 1 outputs the operator number (zero at the start) to

0 blocks 2 and 4. After a time equal to 2 G0, the following clock pulse is applied to the block 3 for selecting simple operators, according to which the number of data arguments K is fed to block 2, and the simple positional operator J that is extracted from complex the operator in block 3 of selection of simple operators on the previous cycle. Data distribution unit 2 transmits the elements of the input set X to

0 output with number i (at the moment of start zero), and block 4 of distribution of operators transmits a simple operator to exit with the same number At time 3 T0 control block 1 gives impulse ri, which

5 starts the first calculation unit 5 and at the same time, by the clock pulse 3G0, data and a simple operator are transferred to the corresponding block 5. By the same pulse, in block 3 of selection of simple operators, the number of arguments is determined and the characteristic number of the next simple operator is selected, which will be transferred to the corresponding blocks at the arrival of the synx® pulse. At the same time, the sync pulse 3 r0 will receive the number of the next block 5 of the calculation in blocks 2 and 4 of the operators.

, To increase the noise immunity between the calculation blocks 5, the elements of AND 6 are enabled, which allow the launch of the corresponding block 5 only in the case when the corresponding clock pulse G | and the previous block 5 produced a result. The device shuts down when the last block 5 returns the result.

Calculation unit 5 operates as follows.

On the leading edge of the starting pulse, a multi-phase generator of the synchronization unit 11 is launched, which produces a series of four pulses of duration 1, T2, Gz, and G4. Simultaneously with the starting pulse, the number of signals representing the values of the bits of the operator is fed to the inputs of the register 9. Next, the read write inputs of registers 7 and 9 are given a pulse, which is used to write input signals to these registers.

After loading the input signals into the register 7, a set of zeros and ones appears at its outputs, which is fed to the inputs of the node 8 for calculating the sum of units. Next, a number containing the sum of units is outputted to the control inputs of the switch 10. Next, the control signal of the switch 10 is supplied with a control signal, from which on the output signal takes the true value. On the fourth pulse of the synchronizer, this synchronizer stops.

Claims (1)

Invention Formula A device for calculating mathematical functions containing a control block and k calculation blocks (where k is the level of a complex operator), with the information output of the a-th calculation block (where, ..., k-1) connected to the first information input (a + 1 the) computing unit, the information output of the k-ro computing unit is connected to the output of the device result, characterized in that, in order to increase speed, it contains a data distribution unit, selection of simple operators, a unit of distribution of simple operators and (k-1) elements And, with the start input, the input of the vector of binary signals and the input of the complex the positional operator of the device is connected respectively to the start input of the control unit, to the information input of the data distribution unit and to the information input of the allocation unit simple operands, from the first to the kth outputs of the control unit are connected respectively to the start input of the first calculation unit and to the first inputs of the AND elements from the first through (k-11th, output of the a-th element AND connected to the start-up input (a + 1) of the calculation block, the output of the readiness flag of the calculation block is connected to the second input of the a-th element I. the output of the readiness sign for-ro calculation block is connected to the reset input of the control unit, (k + 1) the output of which is connected to the inputs of the synchronization of the data distribution unit, the allocation unit of simple operators and the distribution unit of simple operators, (k + 2) -u the output of the control unit is connected to the first control input of the data distribution unit and to the first information input of the distribution unit of simple operators, the second information input of which is connected to the output of a simple positional operator of the selection unit of simple operators, the output of the number of arguments of the simple operator of which is connected to the second control input of the unit data distribution, outputs from the first to the k-th of which are connected respectively to the second information inputs of the computing blocks from the first to the k-th, outputs from the first to the k-th block of the distribution of simple operators are connected respectively to the inputs of the code of simple operators of the computing units from the first to the kth. p y Xn. Q eight B Iz bU R Run Reset i So f in fu D 17 ® / r2