SU855657A1 - Binary multiplier - Google Patents

Description

(54) binary INFINITE / KITEL

one

The invention relates to computing and automation and may

to be applied in devices that perform mathematical operations and in control devices, for example, numerical control devices for machine tools.

A device is known that contains a counter, differentiating cascades, elements of the selection of pulse sequences, an OR element and allowing the frequency of the pulse sequence to be multiplied by a number proportional to the multiplier written in parallel. code i.

However, the use of differentiating cascades is inconvenient with modern element base, except that the output pulses of the multiplier are not synchronized by the pulses of the original sequence, which in some cases requires the introduction of a synchronization device.

The closest in technical essence and the achieved result is the device, containing the source of the original pulse sequence, binary counter, AND elements, OR element, multivibrator, delay elements, feedback trigger, the source of the original pulse sequence being connected to the input of the multiviral, counting input of the counter and to the synchronization input of the feedback trigger, the direct outputs of the counter bits are connected to the first inputs of the elements I, the code bus of the multiplier to the second inputs of the elements And comrade, the multivibrator output circuit to delay elements, the outputs. which are connected to the third inputs of the And elements, the output of the feedback trigger is connected to the fourth inputs of the And elements, and inverse, the counter outputs are connected to the subsequent inputs of the And elements of all subsequent bits 2.

However, this device is complex, has an irregularly sized structure and, moreover, contains elements of support, which makes it difficult to implement with modern element base.

The purpose of the invention is to simplify the device and increase the regularity of its structure.

The goal is achieved by the fact that in a binary multiplier, containing 30 VDI n countable triggers (n is the multiplier width) / first group of elements AND, the first inputs of ix elements AND of the first group (,,., P) are connected to the inputs, respectively (n-i + 1) -x bits of the multiplier code, the second inputs are with zero outputs iX of counting triggers, and the outputs are with corresponding inputs of OR elements, the output of which is the device output, the counting inputs of counting triggers are connected to the direct pulse input multiplier sequences introduced wto and the group of elements is And, with the first inputs ix of elements And of the second group connected to the unit outputs of the corresponding counting triggers, the output of each j-ro element And the second group (j 1, ..., p-1) is connected to the BTopHfJi input (j + 1 ) -ro element AND of the second group, control input (j + 1) -ro of the counting trigger and the third input (J + O-ro element AND of the first group, fourth inputs (j + 1) -x and the third input of the first AND element of the first group connected to the input of the inverse pulse sequence of the multiplier.

Figure 1 shows a diagram of a three-bit single binary multiplier; figure 2 - timing charts of the device when the multiplier code 101.

The device contains counting triggers (TU-triggers) 1/1, ... 1/3, elements AND 2/1 ... 2/3 of the first group, inputs 3/1 ... 3/3 of the code of the multiplier, element OR 4, input 5 of the direct pulse sequence of the multiplicand, elements AND 6/1 ... 6/3 of the second group, input 7 of the inverse pulse sequence. The direct and inverse pulse sequences are formed by the source 8 of the pulse sequence (generator).

The device works as follows.

Upon receipt of signals from the input 5 of the direct pulse sequence to the counting inputs of the triggers, a synchronous binary counter is used, formed by the 1/1 ... 1/3 trigger and 6/1 ... 6/3 I elements. Switching the trigger triggers regardless of the bit number yes it occurs simultaneously on the leading edge of the clock pulse. No more than one trigger is always switched to state 1, since the logical inputs of the subsequent triggers are sent to the enable inputs. Accordingly, the arrival of the signal lines 1 simultaneously to the second and third inputs of elements AND of the second group is possible only for one of the elements 2/1. .. 2/3, namely for that element, the second input of which is connected to the inverse output of the trigger, which is in the O state, and the third input - to the permissive input of the same trigger, to which the signal 1 arrives at this moment. Therefore, the pulses give out e with the elements 2/1 2/3 ... And entering 5 at their inputs signals 7 input pulse sequence do not coincide in time. The first inputs 3/1 ... 3/3 of the elements And 2/1 ... 2/3 receives the multiplier code allowing

o operation of those of them, where in the corresponding code bits there is 1. The average frequency f of the total pulse sequence formed at the output of the element OR 4, in

5 in the general case for an n-bit binary multiplier is

N,

2i

where fg is the frequency of the pulsed signals

sequences; N is the multiplier code value. The operation of the device is explained by time diagrams 5 (Fig. 2), where 9 is the time diagram of the pulse

multiplicative sequence at the input 5 of the multiplier, 10-time diagram of the pulse sequence at the input 7 of the multiplier, 11 timing diagram of the direct output

trigger 1 / 1J 12 - timing of the output element and 6/1; 13 is a time chart of the output element And 2/1; 14 is a timing diagram of the output of the trigger 1/2 15 a timing diagram of the output of the element And 6/2, 16 is a time diagram of the output of the element. And 2/2; 17 - time diagram of the straight output of the trigger 1/3, 18 - time diagram of the output of the And 6/3 element; 19 - the time diagram of the output element And 2/3; 20 is a temporal diagram of the output element OR 4.

The advantages of the proposed binary multiplier over the known ones are the simplification of the circuit and the reduction in the number of components by using the same elements for generating transfer signals in a synchronous binary counter and generating bit pulses; regularity of the binary multiplier structure, which facilitates its hardware implementation.

Forglula Invention

A binary multiplier containing n counting triggers (n is the multiplier of the multiplier), the first group of elements AND, the first inputs i X of the elements AND the first group (i "1, .... N) are connected to the inputs respectively (n-i + l ) - x bits of the multiplier code, the second inputs with zero outputs of the i-th counting flip-flops, and the outputs with the corresponding inputs of the OR element whose output is the output of the device, the counting inputs of the counting flip-flops are connected to the input of the direct pulse sequence of the multiplier, differing from that in order to simplify and enhance the regularity of the binary multiplier structure, the second group of elements AND is entered into it, the first inputs of the i-X elements of the second group are connected to the unit outputs of the corresponding counting triggers, the output of each j-ro element of the second group (, ..., p-1) is connected

with the second input (i +) - ro of the element AND of the second group, the input of the 1in (j + 1) -ro counting trigger and the third input of the (j + l) -th element And the first of the group the fourth inputs (j + 1) -x and the third the input of the first elements And the first group is connected to the input of the inverse pulse sequence of the multiplier.

Sources of information taken into account in the examination

1. Author's certificate of the USSR 308523, cl. G About F 7/52, 1969.

2. US patent number 3414720,

cl. 235-164, published. 1964 (proto-type).

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Claims (2)

Claim A binary multiplier containing η countable triggers (n is the width of the multiplier), the first group of AND elements, with the first inputs ί = x of the AND elements of the first group (J 1,... Η) connected to the inputs, respectively (n-1 + 1) -th digits of the multiplier code, the second inputs are 5 with the second input of the (j + Ι) -th element with zero outputs of the i-th counting triggers, and the outputs are with the corresponding inputs of the OR element, whose output is the output of the device, the counting inputs of the counting triggers are connected to input direct pulse sequence of the multiplier, revealing the fact that, in order to simplify and improve the regularity of the structure of the binary multiplier, a second group of AND elements is introduced into it, and the first inputs of the i-th elements of the second group are connected to the unit outputs of the corresponding countable triggers, the output of each j-ro element AND of the second group (j = 1, ..., n-1) is connected And the second group, the control input (j + 1) -ro of the counting trigger and the third input of the (j + 1) -th element of the first group, the fourth inputs (j + 1) -x and the third input of the first elements of the first group are connected to the input inverse pulse multiplier sequence. . - Sources of information, ' ^υ taken into account in the examination 1. USSR Copyright Certificate No. 308523, cl. G 06 F 7/52, 1969. 2. US Patent No. 3414720, cl. 235-164, published. 1964 (proto15 type). Yag (rig! J ~ n_l_p__p figure 2