SU1003315A1 - Device for control of pulse repetition period - Google Patents

Description

The invention relates to a pulse technique and can be used in simulators of signals of frequency sensors, automation, software control systems.

A code to pulse frequency converter is known, which contains a reference frequency generator, a device for changing the pulse frequency according to a quadratic hyperbola, a pulse counter, potential pulse valves, and an input code register 1. 3 The disadvantage of the converter is a low frequency setting accuracy depending on the nonlinear accuracy. quad and discreteness of the reference frequency setting.

Known generator with programmed control, containing the counter; accumulator register, second counter, comparison circuit, distributor providing the formation of various pulses 2 J.

The disadvantage is the low accuracy of setting the pulse frequency.

The purpose of the invention is to improve the accuracy of setting the following frequency

pulses by increasing the discreteness of setting the period values.

The goal is achieved by the fact that in a device for controlling the pulse following period, containing a pulse counter, a code matching unit, one group of inputs of which is connected to the outputs of the pulse counter, and the other group

10 inputs are connected to the outputs of the memory register bits, a step delay line, a selector-multiplexer, an adder are additionally introduced, and the input of the step 15 hold line is connected to the output of the code matching unit and the input of the selector multiplexer, the remaining inputs of which are connected to the taps of the step delay line, input management

The 20 selector-multiplexer is connected to the low-order bit of the memory register, and the output is connected to the enable input of the memory register, while the outputs of the adder are connected in parallel to

25 inputs of the memory register, the inputs of the adder are connected to the outputs of the bits of the memory register.

The drawing shows the functional diagram of the device for controlling the pulse following period.

The device for controlling the pulse pulse period comprises a pulse counter 1, a block 2 of codes, a memory register 3, a step 4 delay line 4, a multiplexer 5 and an adder 6, a bus

7 pulses of exemplary frequency, bus

8 binary-decimal (And + 1) -disc codes of the period of the generated pulse frequency.

 The device works as follows.

Counter 1 performs a continuous counting of the number of pulses of the exemplary frequency fo, coming through bus 7, arriving at its input. When the codes at the output of counter 1 and AND of the higher binary-decimal bits of register 3 memory match, the code matching unit 2 generates a pulse, which is fed to the input of delay line 4, performing a successive pulse delay of

- y, where T ,, is the period of the pulses of the exemplary frequency fo, th line number of the line 4 delays. The total delay time is 9 Td / U. Depending on the value of the additional binary-decimal bit with a 10 TQ 3 register weights, the selector-multiplexer 5 transmits to the device’s output a pulse from one, from the delay line 4 delays (or directly from the output of the 2 coincidence unit, if m 0 ) held at time With the appearance of each pulse at the output of the selector-multiplexer 5, the register 3 is typed (n + 1) -digit binary-family code from the output of the adder 6, which is the sum of the values of the period code of the generated frequency NY in this m The time and state register memory register 3 at the time immediately preceding the rewriting process. In memory register 3, sequential accumulation of cue code occurs, equal to the value of the period of the generated frequency from bus 8, which in general can be changed to obtain a smooth (or intermittent) change in the generated frequency. In the process similar to the copying of a code with a frequency f in the counter 1, the block 2 of coincidence of the codes produces pulses after an interval

time, equal to the integer values of a given period T, discretized to the nearest tenths () is performed by means of a delay line 4 and a selector-multiplexer 5, controlled by an additional register bit 3. When the control code N is changed (bus 8), the device runs to the end of the previous value of the period following the weekend

pulses, and the duration of the subsequent period is already determined by the new value of N, which makes it possible to smoothly (with discreteness TQ) change the frequency of the next INP pulses with a corresponding change in the N code at the device input.

Thus, the proposed device, compared with the known,

allows you to improve the accuracy of setting the pulse frequency without increasing the sample frequency. Claims An apparatus for controlling the pulse pulse period comprising a pulse counter, a code matching unit, one group of inputs of which is connected to the outputs of the pulse counter, and another group of inputs of connecting with the outputs of the memory register bits, characterized by the fact that, in order to increase the accuracy of the frequency, a step delay line, a multiplexer, an adder, and an input the step delay line is connected to the output of the code match unit and the selector-multiplexer input, the remaining inputs of which are connected to the taps of the step delay line, the selector-multiplexer control input is connected to the low register bit, and the output is connected to the enable memory register input, when In this case, the outputs of the adder are connected in parallel to the inputs of the memory register, and the inputs of the adder are connected to the outputs of the bits of the memory register. Sources of information taken into account in the examination 1. USSR author's certificate number 494847, cl. H 03 K 13/02, 03/08/73. 2. Authors certificate of the USSR 743176, cl. H 03 K 3/64, 06.12.77.

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Claims (1)

The claims · A device for controlling the pulse repetition period, comprising a pulse counter, a code matching unit, one group of inputs of which is connected to the outputs of the pulse counter, and the other group of inputs is connected to the outputs of the bits of the memory register, characterized in that, in order to increase the accuracy of jamming frequency, a step delay line, a selector multiplexer, an adder are introduced into it, and the input of the step delay line is connected to the output of the block of coincidence of codes and the input of the selector-multiplexer, the rest whose inputs are connected to the taps of the stepped delay line, the control input of the selector-multiplexer is connected to the least significant bit of the memory register, and the output is connected to the enable input of the memory register, while the adder outputs are connected in parallel to the inputs of the memory register, and the adder inputs are connected to the outputs of the register bits memory.