SU828391A1 - Device for controllable delay of pulses - Google Patents

Description

one

The invention relates to a pulse technique and can be used in measuring and computing devices.

Known devices of controlled delay pulses, containing a generator of counting pulses, a first trigger, a decoder zero, the output of which is connected to a single input of the first trigger, a reversible counter, the outputs of which are connected to the outputs of the decoders zero, the first logical element And connected to the source of delayed emulsions by the first input , the second input - to the output of the generator of counting pulses, and the output - to the summing input of the reversible counter, the second logical element And, connected by the first input to the zero in the first trigger, the second input to the output of the counting pulse generator, and the output to the subtractive input of the reversible counter, the second trigger, the zero input of which is connected to the source of delayed pulses, the third logical element I, the first input of which is connected to the zero output of the second trigger, and the second input is connected to the output of the generator of counting pulses, the source of control pulses 1.

Such controllable delay devices do not automatically control the delay time of input pulses during interpulse intervals. A controlled delay device is known comprising a counting pulse generator and two identical channels: a delayed pulse channel and a delay control channel; with each channel

includes a reversible counter, the summing and subtracting inputs of which are connected to the outputs of the first and second logical elements And, respectively, the first input of the second logical element And

connected to the generator of counting pulses, and the second input is connected to a trigger, the first input of which is connected to the output of the decoder zero, the inputs connected to the outputs of the counter, and the decoder is zero

The delay control channel is connected to the second trigger input of the delayed pulses channel, and the second trigger input input of the delay control channel is connected to the source of the delayed pulses 2.

This device has a reduced speed, because it does not allow to submit another delayed pulse until the previous delayed pulse is formed at the output, and

introduce another duration impulse

Delay until the formation of the previous delayed pulse.

The aim of the invention is to increase speed.

This goal is achieved by the fact that the controllable pulse delay device contains a counting pulse generator and two identical channels: a delayed pulse channel and a delay control channel, each channel including a reversible counter, the summing and subtracting inputs of which are connected to the outputs of the first and second logical elements And, the first input of the second logical element And is connected to the generator of the counting pulses, and the second input - with the trigger output, the first input of which is connected to the output of if the zero input is connected to the output of the counter, the second trigger input of the delayed pulses channel is connected to the output of the decoder zero of the delay control channel, and the second trigger input of the delay control channel is connected to the source of hidden pulses, a counting unit is inserted into each channel, three additional logic elements And, the additional trigger and pulse shaper, while the input of the counting unit through the first and second logic gates connected in series connected to the output of the counting pulses generator, and the output of the counting unit is connected to the input of one of the bits of the reversible counter and to the first input of the additional trigger, the first output of which is connected to the second input of the second additional logic element I; The second output of this trigger is connected to the first input of the first main logic element And, the second input of which is connected to the output of the first additional logic element And, and the second input of the additional trigger is connected to the second input of the first additional logic element And through the pulse shaper and the third additional logic element And, the second input of which is connected to the output of the main trigger channel; In addition, the input of the pulse generator of the channel of the delayed pulses is connected to the source of delayed pulses, and the input of the generator of the pulse of the delay control channel of the channel is connected to the source of control pulses.

The introduction of new elements and connections allows to increase the speed of the device controlled delay pulses.

The drawing shows the functional electrical circuit of the device.

The controllable pulse delay device comprises a counting pulse generator 1 connected to the first inputs of logic gates AND 2-5. The output of the logical element And 2 through the logical element And 6 is connected to the summing input of the reversible counter 7, the subtractive input of which is connected to the output of the logical element And 3, and the outputs of the bits through the decoder zero 8 are connected to the zero input of the trigger 9, the single output of which is connected to the second the input of the logical element And 3, with the output of the device 10 and with the first input of the logical element And 11. The second input of the logical element And 11 through the pulse shaper 12 is connected to the second input of the element 2 and to the input 13, on which stray delayed pulses; the output of the element 11 is connected to the single input of the trigger 14. The zero output of the trigger 14 is connected to the second input of the element 6, the single output to the first input of the logic element 15, the second input of which is connected to the output of the element 2, and the output to the input of the counting block 16. The output of the scaling circuit 16 is connected to the input of one of the last stages of the reversible counter 7 and to the zero input of the trigger 14. Elements 2, 3, 6-16 and the connections between them constitute a channel of delayed pulses.

The output of the logic element And 5 through the logic element And 17 is connected to the summing input of the reversible counter 18, the subtractive input of which is connected to the output of the logic element And 4, and the outputs of the bits through the decoder zero 19 are connected to the zero input of the trigger 20, the single output of which is connected to the second the input of the logic element 4 and the first input of the logic element 21. The second input of the logic element 21 and 21 through the pulse shaper 22 is connected to the second input of the element 5 and to the input 23, which receives control pulses eni; the output of the element 21 is connected to the single input of the trigger 24. The zero output of the trigger 24 is connected to the second input of the element 17 and the single output to the first input of the logic element 25, the second input of which is connected to the output of the element 5, and the output to the input of the scaling unit 26. The output of the scaling unit 26 is connected to the input of one of the last stages of the reversible counter 18 and to the zero input of the trigger 24. Elements 4, 5, 17-26 and the connections between them constitute the control pulse channel.

In addition, the single input of the trigger 20 is connected to the input of the delayed pulses 13, and the single input of the trigger 9 is connected to the output of the decoder zero 19.

In the initial state, the signals at inputs 13 and 23 are absent; therefore, the pulses of the generator 1 do not pass through the logic elements 2 and 5; the triggers 9 and 20 are in the zero state, therefore, the pulses of the generator 1 through the logic elements And 3

and 4 fails to pass. Triggers 14 and 24 are in the zero state, in which the "enabling voltage is applied to the logic elements AND 6 and 17. The conversion blocks 16 and 26, like the reversible counters 7 and 18, are in the original zero state.

The operation of the device begins with the arrival at the input 23 of a rectangular control pulse, the duration of which is equal to the required delay time T3 ,. This pulse arrives at the input of the AND 5 logic element, allowing the passage of pulses from the generator 1 through the AND 17 logic element to the summed, reverse input of the counter 18. Thus, the control signal is converted into pulses whose number is proportional to the required delay time. This number of pulses is recorded in counter 18 as a code and can be stored for as long as necessary.

After setting the required delay time, the device is ready to receive a delayed pulse. A rectangular impulse that needs to be delayed is fed through input 13 to the logical element I 2, from which the generator 1 pulses through the logical element 6 receives the summing input of the reversing counter 7. Thus, the delayed signal is converted into pulses proportional to the duration of the delayed pulse. This number is stored as a code in counter 7.

At the same time, a delayed pulse from input 13 arrives at the single input of the trigger 20 and translates it into a single state, in which the "permitting voltage" appears at the output of the trigger. Under the action of this voltage, the logical element 4 transmits to the subtracting input of the counter 18 the pulses of the generator 1. After the number of pulses becomes equal to the number of pulses entered earlier on its summing input, the counter 18 goes to the initial zero state and at the output of the zero decoder 19 an impulse appears. This impulse arrives at the zero input of the trigger 20, returning it to the initial zero state, and to the single input of the trigger 9, transferring the latter to the single state, in which the “permitting voltage” appears at the input of the logical element 3. Through the element 3 opened by this voltage, the pulses from the generator 1 are fed to the subtractive input of the reversible counter 7. After the number of these pulses is equal to the number of pulses entered earlier on its summing input, the counter 7 goes to the initial zero state, and at the output of the decoder zero 8 appears pulse. This impulse arrives at zero

trigger input 9, returning it to its original state. The device returns to its original state, forming at output 10 a rectangular pulse equal in duration to the delayed pulse input to input 13, but delayed relative to the latter.

For the delay of the next pulse, the next pulse must be fed to the input 23, providing the necessary delay time. If this control pulse arrives at the input 23 after the wake-up signal of the beginning of the delayed pulse at the output of the decryptor zero 19, the delay control channel operates as it was described above. But the proposed device, unlike the prototype, allows to give a regular control impulse before the appearance of a signal from the zero decoder 19.

In this case, the pulse shaper 21 generates a short pulse at the moment the control pulse starts. This impulse through the logical element AND 21, on the control input of which there is a "permitting voltage from the output of the trigger 20, is fed to the single input of the trigger 24. The trigger 24 is transferred to the unit state, in which the" enabling voltage is removed from the logical element And 17 and is applied to the logic element And 25. The control pulse opens the logic element And 5, and the pulses of the generator 1 through the logic elements And 5 and 25

enter the input of the counting unit 26, which starts counting pulses.

The scaling unit 26 (and, similarly to it, scaling circuit 1 works in the same code as the reversible counter 18 (7), but

has fewer bits than counter 18 (7). An admissible corresponding recalculation scheme has n bits. Then the output of this scaling circuit is connected to the input of the n-1-th digit of the corresponding

reversible counter. At the same time, the maximum number of pulses that the scaling circuit can take before overflow should be less than the number of pulses of the generator 1, placed at the minimum duration of the pulses fed to the input of the corresponding channel of the device.

While the counting unit 26 counts the pulses of the generator 1, the process is completed

subtracting in the counter 18, the decoder zero 19 is triggered and, as was described above, the formation of the next delayed pulse begins in the channel of the delayed pulses. At the time when the number of pulses arriving at the input of the scaling circuit is compared with the recalculation coefficient of this circuit, it overflows, switches to the initial state, and a pulse is generated at its output.

Claims (2)

This impulse goes to the n + 1-th counter of the reversible counter, writing down the unit in this bit, and to the zero input of the trigger 24, transferring it to the zero state, removing the "voltage permitting voltage from the logic element I 25 and supplying the AND 17. Therefore, the subsequent pulses of recording the delay interval from the output of element 5 are already sent to the summing input of the reversing counter 18, and by the time the control pulse ends, the counter corresponding to the next time will be fixed in the counter Delay Tz, although the counter did not take part in fixing this interval for a part of this time. Similarly to the operation of the delay control channel, elements of the delayed pulses channel work when the next delayed pulse arrives at the input 13 during the formation of a delayed output pulse by the channel. As follows from the above, the proposed device has a higher speed than the prototype, since, unlike the latter, it allows to send control signals before the process of forming the next delayed output pulse and to give delayed pulses before the end of this process. Claims An impulse controlled delay device comprising a counting pulse generator and two identical channels: a delayed pulse channel and a delay control channel, each channel containing a reversible counter, the summing and subtracting inputs of which are connected to the outputs of the first and second logic elements, respectively, and the first input the second logic element And is connected to the generator of the counting pulses, and the second input - with the output of the trigger, the first input of which is connected to the output of the descriptor zero, in Dami connected to the outputs of the counter, while the second input of the trigger dripped delayed pulses connected to the output of the decoder zero channel control delay, and the second input of the trigger channel control delay connected to the source of delayed pulses, characterized by the fact that, in order to improve speed, in each channel entered scaling unit, three additional logic gates And, additional trigger and pulse shaper, while the input of the scaling unit through the first and second connected in series Additional logic elements I are connected to the generator of counting pulses, and the output of the counting unit is connected to the input of one of the bits of the reversible counter and to the first input of the additional trigger, the first output of which is connected to the second input of the second additional logic element And, the second output of this trigger is connected to the first input of the first main logic element And, the second input of which is connected to the output of the first additional logic element And, and the second input of the additional trigger is connected to The second input of the first additional logical element And through the pulse shaper and the third additional logical element And, the second input of which is connected to the output of the main trigger channel; In addition, the input of the pulse generator of the channel of the delayed pulses is connected to the source of delayed pulses, and the input of the generator of the pulse of the delay control channel of the channel is connected to the source of control pulses. Sources of information taken into account in the examination 1. USSR author's certificate number 396822, cl. And OZK 5/153, 08.23.71. 2. Author's certificate of the USSR № 573865, cl. S OZK 5/153, 04.04.75 (prototype).