SU661814A1 - Ring counter - Google Patents

Description

The invention relates to the field of computing and automation and can be used in various devices for discrete information processing.

Known ring counters containing ring frequency dividers 1.

The disadvantage of such ring meters is limited functionality.

Also known is a ring counter containing an annular divider, the output of which is connected to the inputs of the control unit for initial states 2.

The disadvantage of this ring counter is also its limited functionality.

The aim of the invention is to expand the functionality.

The goal is achieved in that a ring counter, which contains a ring divider, the outputs of which are connected to the inputs of the initial state control unit, is additionally entered a descriptor, a transfer control unit and a ring communication unit, with the forward and inverse outputs of the annular divider connected to the decoder inputs whose outputs are connected

T

with the inputs of the transfer control unit, the control inputs of which are connected to the addition and subtraction buses, and the outputs of the transfer control unit are connected to the inputs of the ring splitter, the output of the initial control, the states connected to the yn,:: control input of the ring communication unit The information input of which is connected to the last output of the annular divider, and the auxiliary inputs of the annular communication unit are connected to the outputs of the decoder and the subtraction tin, the outputs of the annular communication unit are connected to the control inputs of the annular division it is

The drawing shows a block diagram of a ring counter.

The ring counter contains a ring

5 divider 1, the outputs of which are connected to the inputs of the control unit 1 of the initial states 2, direct and inverse, the outputs of the annular divider 1 are connected to the inputs of the decoder 3, the outputs of which are connected to the inputs of the control unit, by transfer

0 4, the control inputs of which are connected to the addition and 5 subtraction buses 6, and the outputs of the transfer control unit 4 are connected to the inputs of the ring splitter 1, the output of the initial states 2 control unit is connected to the control input of the ring communication unit 7, whose information input connected to the last input of the ring splitter 1, and the auxiliary inputs of the ring communication unit 7 are connected to the outputs of the decoder 3 and the subtraction bus 6, the outputs of the ring communication unit 7 are connected to the control inputs of the ring splitter 1. An annular divider 1 is placed, the forward and inverse outputs of which are connected to the decoder 3. The table below shows the obtaining of weights from "O to" 2L-1 in the decoder 3. 1. From the decoder 3, the weighting factors from "O to" 2 are fed to control unit 4. transfer in accordance with the table. 2. In table. 2 shows the states; the outputs of the annular divider within the full cycle of addition (from left to right) and subtraction (from right to left). The transfer control unit 4 is supplied with an addition bus 5 and a subtraction layer 6. The outputs of block 4 are connected to the inputs of the annular divider 1. The inverse outputs of the annular divider 1 are inputted to the unit 2 of the control of initial states, the output of which is fed to the annular communication unit . To the ring communication unit 7, the weight coefficients " b and n & n + 1 are supplied with descrambled Ring counter operates as follows. At the initial moment, all the outputs of the ring splitter 1 are in the "On state" and from the output of the decoder 3 to the transfer control unit 4, the resolution level is received, corresponding to the weighting factor "O." Simultaneously from block 2, the control of the initial states through block 7 of the ring link enters the permitting level at the control inputs of the first and last trigger cell of the ring divider 1. In addition mode on bus 5, the pulse goes through block 4 of the transfer control to the first counting input of the ring divider 1 which changes its state, and from the output of the decoder 3 to the transfer control unit 4661814, the resolution level arrives corresponding to the weighting factor "1. With the arrival of the following pulses at the entrance of region 5, the process is repeated for all weights. At the end of the addition cycle, the transfer control unit 4 allocates a 2n pulse via bus 8 for the next group of scaling circuits. In read mode. at the position corresponding to the weighting factor "O decoder 2, bus 6 drives the pulse through the transfer control unit 4 to the counting input of the ring divider 1, which changes its state, and from the output of the decoder 3 to the transfer control unit 4 the permitting level corresponding to the weighting factor 2p-1. At the same time, a loan impulse is formed along the bus 9 from the next group of scaling circuits. If the process is repeated for all weights in the addition mode with the arrival of subsequent pulses at the entrance of section 5, then in the subtraction mode when weighting coefficients are formed. "O," and and "2n-1 of the weighting factors," 1, "n + 1 and" 2ff, respectively, the counter works as follows. The subtraction pulse from the tire 6 passes through the transfer control unit 4 to the counting; The ring-splitter 1 inputs simultaneously and simultaneously to the ring coupling unit 7. The ring coupling block 7 from the decoder 3 is supplied with resolution levels corresponding to the weighting factors "1 or" N + 1, which fall on the control first and last inputs of the ring divider 1, give permission for the passage of the subtraction pulse. The use of reversible control of the decompression state of the bits of the ring divider provides the main advantage of these counters - the simplicity of resolution and speed, which expands the functionality of annular dividers. The use of the reversing board increases the load utilization of the trigger cells of the ring division and makes it possible to use a number of coefficients as controllers. signals for further processing of information.

661814 Table

n

n +1

2 "-l

Outputs

Input pulse number

O1

OO

OO

OO

OO

Claims (2)

addition Claims An annular counter comprising an annular divider, the outputs of which are connected to the inputs of an initial state control unit, characterized in that, in order to expand its functionality, a decoder, a transfer control unit and a circular link unit are additionally introduced into it. the inverse outputs of the ring splitter are connected to the inputs of the decoder, the outputs of which are connected to the inputs of the transfer control unit, the control inputs of which are connected to the add and subtract buses, and the outputs of the block transfer controls are connected to the ring splitter inputs, the output of the unit Q 5 Orr-i Qn-i On t a b l and D a 2 Ooh About 1 1 1 oo oo 0o 1o one the subtraction control of the initial states is connected to the control input of the ring communication unit, the information input of which is connected to the last output of the ring divider, and the auxiliary inputs of the ring communication unit are connected to the outputs of the decoder and the subtraction bus, the outputs of the ring communication unit are connected to the control inputs ring divider: Sources of information taken into account during the expert review 1. USSR author's certificate No. 514443, cl. H 03 K 23/02, 1975. 2. Laneov L. L. and others. Digital frequency dividers on logic elements. “Energy M., 1975, p. 73, fig. 3-16. Crush Q, Sn8iS2- -tt-ttt g 1 1L , -t