SU748419A1 - Device for determining arithmetic mean - Google Patents

Description

(54) DEVICE TO DETERMINE THE AVERAGE

one

The invention relates to the field of computer technology, to specialized devices for processing statistical experimental data.

A device for determining a moving average 1 is known, which contains a memory block, an adder, a reversible counter, and a strobe block. control unit. About

The closest in technical solution is a device for determining the arithmetic average containing a reversible counter, elements AND, a delay element, a counter, 15 a pulse generator, a memory block 2.

A disadvantage of the known devices is the low speed and accuracy, as well as the complexity of the equipment-20 implementation.

The aim of the invention is to improve the accuracy, speed and simplification of the device,

For this purpose, a register, a digital comparator, and a synchronization block are entered into the device for determining the arithmetic average value of 25, and the first output of the synchronization block is connected to the second time input — the offset

Pulse converter to the control inputs of the register and the memory block, the outputs of which are connected to the first information inputs of the digital comparator, the second information inputs of which are combined with the information inputs of the register and connected to the corresponding outputs of the counter, the counting input of which is combined with the first inputs of the second and third And elements and is connected to the output of the delay element, the input of the delay element is combined with the control input of the digital comparator and connected to the output of the first element And, second Its input is connected to the second output of the synchronization unit, the output of the pulse generator is connected to the third input of the time-pulse converter, the second output of which is combined with the control input of the register and connected to the first input of the synchronization unit, the second input of which is connected to the output of the digital comparator, the third and the fourth outputs of the synchronization unit are connected respectively with the second inputs of the second and third elements And, the output of the third element, And connected to the input of the reversible counter, the output to The second element I is connected to the input of the calculation of a reversible counter, the outputs of which are the outputs of the device. The block diagram of the device is shown in the drawing. The device contains a time-pulse converter 1, a sync block 2, a delay element 3, the first second and third elements AND 4, 5, 6, the pulse generator 7, the reversible counter 8, the counter 9, the register U, memory block 11 and digital comparator 12 .; The device works as follows. In the initial state, the reversible counter 8, the register 10 and the cells of the memory block 11 are cleared. At the time of starting block 2, it generates a pulse at the first output, the counter 9 is set to zero, the contents of the memory block 11 are shifted and the start time of the pulse converter is signal from the second output - opens the element And 4. The first impulse from the output And 4 passes through the digital; comparator 12 to the second input of the synchronization block, as a result, there is a HIGH potential at the third output of block 2. At the same time, the pulses from the output of AND 4 will be fed to the counting input of counter 9 and to the summing input of the reversing counter 8. By the time when the time-pulse converter 1 will form a pulse on the second output, the number of pulses, behind a fixed counter 9 and a reversive NW meter counter 8, will be proportional to the input signal, i.e., will, on some scale, represent the first sample number. An impulse. From the second time-output impulse converter will put this number into the register 10. After some time, a second impulse will appear at the first output of the control unit 2 and the actions described cycle: sec j J turn. This will continue until all the cells of memory block 11 have been filled, i.e., until the first sample of numbers X,, | . 1,2, .. , P . In this case, on the reversible counter 8, all the numbers in the sample will be fixed to the suglma, representing - on some scale - their arithmetic average. After that, the outputs of the memory block 11 will contain the number X, and the digital comparator 12 in the next cycle of the device will pass a pulse to the second input of the synchronization unit only when the number in the counter 9 becomes equal to X. The following options are possible:) P

Claims (2)

748419 In the first case, from the moment the equalities are reached, X will open, similarly to the one described above, element 5, and the pulses arriving at counter 9 will also be summed by reversing counter 8 until the number x is formed, i.e. until there is a pulse at the second time-pulse output. converter Consequently, a value will be added to the reversible counter 8, which is obviously equivalent to subtracting the value of H from its content and adding the value of Xj. . An impulse from the second output of the time-pulse converter will put the number x. register 10, and the next impulse from the first output of the synchronization block will write it to the place of the number X in the memory block, the outputs of which will have the number X a, etc. In the second case, the first impulse comes to the first input of the synchronization unit, but the impulse it arrives at the second input earlier; at least one impulse will have time to go to counters 8 and 9, thus, the contents of the reversing counter 8 does not change, otherwise the circuit works in the same way as described. Finally, in the third case, the turn of the pulse at the first input of the synchronization unit. It transfers the formed XP number to register 10 and will cause the appearance of a single potential at the fourth output of the synchronization unit, i.e. from this moment, the pulses arriving at the input of counter 9 will be subtracted from the contents of the reversible counter 8. This will continue until. until the equality S - is reached, digital comparator 12 will skip the impulse to the second input of block 2, stopping the indicated subtraction. As a result, the contents of the reversible counter 8. will decrease by the value of / d -% f, which is obviously equivalent to subtracting the number from it (. and adding the number 5 (n +... In the future, the scheme works the same way, with the difference that the numbers k, X; ..., and in the role of Xn-v / - the numbers g "" It is easy to see that the contents of the reversible counter 8 will change in the course of forming the next sample number (if it is more replaceable),: Or } a short time after its formation (if it is less replaceable), therefore the contents of counter 8 will be continuous clearly and accurately track the arithmetic mean of a sliding sample, without any jumps and spikes in the prototype circuit. Adding and subtracting time losses that are significant in the prototype circuit are minimized here. Simplification of the device, improvement in accuracy and speed will allow to improve the characteristics of computing and control systems containing the device, and thereby obtain a positive economic effect. The invention The device for determining the arithmetic mean, containing a reversible counter, AND elements, delay element, counter, pulse generator, memory block, time pulse converter, the output of which is connected to the first input of the first AND element, the first input time-pulse converter input device, in the sense that, in order to improve the accuracy and speed of the device, a register, a digital comparator and a synchronization unit are entered into it, the first output of the synchronization unit On the switch to the second input of the time-pulse converter, to the control inputs of the register and the memory block, the outputs of which are connected to the first information inputs of the digital comparator, the second information inputs of which are combined with the information 9. 6 The main inputs of the register and connected to the corresponding outputs of the counter, the counting input of which is combined with the first inputs of the second and third elements AND and connected to the output of the delay element, the input of the delay element combined with the control input of the digital comparator and. connected to the input of the first element I, the second input of which is connected to the second output of the synchronization unit, the output of the pulse generator is connected to the third input of the time of the pulse converter, the second input of which is combined with the control input of the register and connected to the first input of the synchronization unit, the second input of which is connected to output of the digital comparator, the third and fourth outputs of the synchronization unit are connected respectively to it by the second inputs and the third And elements, the output of the third And element is connected to the input from dix down counter, the output of the second AND element is connected to the input of subtraction down counter whose outputs are the outputs of the device. Sources of information taken into account in the examination 1. Copyright certificate for 2394955 / 18-24, from 09.09Л976. 2. USSR author's certificate number 278227, M class. G About F 15/36, 1970. (prototype). . 748419