SU528695A1 - Pulse frequency multiplier - Google Patents

Description

one

The invention relates to automation and numerical technology and can be used to reduce the dynamic error and expand the dynamic range when the pulse frequency is multiplied.

A device is known to multiply the frequency of a pulse sequence, based on inverse-proportional conversion to a frequency of a code proportional to the period of the input frequency, reduced by a number of times, equal to the multiplication factor and containing the series-connected driver, multiplier and converter 1.

The closest software of technical dryness to this invention is a pulse frequency multiplying device containing a humor frequency generator, a control unit, two frequency dividers, each of which consists of a subtracting counter and a memory register connected via a code input gate, the control input of which connected to the output of the subtracting counter, and a summing counter, the code output of which is connected to the memory register of the first frequency divider through the code transfer valve, the output being the reference frequency generator is connected to the input of the subtractor counter of the first frequency divider directly, and to the counting input

2

totalized counter-through the second frequency divider, the installation input of which is connected to the terminal of the input signal 2.

The drawbacks of these devices are the delay for the current period, the limited dynamic accuracy decreasing with an increase in the rate of change of the input signal, and the narrow dynamic range of application, mainly for slowly changing input signals.

The aim of the invention is to increase the speed and accuracy of the device.

For this, two additional frequency dividers, a switching element, a frequency subtraction unit, a frequency multiplier, a frequency summing unit, a trigger and additional code transfer gates are entered into the device, with the output of the first frequency divider and the output of the first additional frequency divider connected to the inputs of the subtractor through the switching element frequency, the output of which is connected via a trigger to the first input of the frequency summing unit and through the second additional frequency divider to the first input of the frequency multiplier, which is connected to the second input of the frequency summation unit, the third input of which is connected to the output of the switching element, the control input to the sign output of the subtraction unit and the frequencies, and the output is the device output, while the output of the reference frequency generator is connected to the pulse input; the frequency divider and to the second input of the frequency multiplier, and the installation inputs of the additional half-frequency dividers are connected to the code output of the totalizer via the full-voltage non-transfer gate valves, The main inputs of which are connected to one output of the control unit, the other outputs of which are connected to the control inputs of the frequency multiplier and switching element, | Reset inputs of the summing counter and memory registers of the first and two additional frequency dividers.

The drawing shows a structural electrical circuit of the device.

The device contains a generator 1 reference frequency; four frequency dividers .2-5, ka; each of which consists of a subtracting counter 6, a memory register 7 and a code 8 gate 8, but the number of bits of the counter and a register, summing the counter 9 pulses; eeHTH ii 10-12 transfer code in frequency dividers 3, 4, 5; switching element 13; block 14 vychggapi frequencies; multiplier 15 frequency; a frequency addition unit 16; control block 17 and trigger 18 with a counting input.

The device works as follows.

The output pulses of oscillator 1, which follow with high frequency / o, are fed to the inputs of subtractive counters in frequency dividers 2, 3 and 4, as well as to the input of the counter-divider in multiplier 15, which acts as a frequency integrator. In the memory register of frequency divider 2, the code for the multiplication factor K, which is for frequency divider 2, is introduced. The division factor is entered. At the output of frequency divider 2, pulses are formed, which follow with a frequency

f / o

These pulses arrive at the counting input of the summing counter 9, to the discharge input of which the control signals are received from the control unit 17. In the control unit, the input frequency / l pulses (O generate signals controlling the sequence of operation of all units of the device. The reset signals to summing counter 9 are received at the arrival of each input frequency pulse, as a result of which the counting counter 9 counts the pulses of the input frequency over time equal to the period of the input frequency, and a code proportional to the period of the input frequency

.IO- | --7. (0.

This code every time before resetting the totalizer 9 on the control signals

from block 17 is rewritten to pre-clear, the memory registers of the frequency divider o and one of the frequency dividers 3 or 4 are dependent; on the memory of which of them is stored a code proportional to the previous period. If the code of the previous period is recorded in the memory of frequency divider 4., then the code of the next period LT will be stored in the memory of frequency dividers 3 and 5. The return code Nil from memory register 7 frequency divider 3 with each pulse from the output of the reading counter 6 through gates 8 is written into this counter, initially set to the position (n-number of counter bits). After writing down from the subtracting counter 6 the code written into it with impulses of the input frequency / o oscillator 1, the output of the subtracting counter 6 appears a new pulse repeating the division process. The pulses on the output of the subtracting counter 6 will appear with a frequency

FAti) ..

(3)

Tl

Thus, at the output of the frequency divider 3, a frequency is formed that is increased К K times compared to the input.

To obtain a frequency proportional to the derivative of the input signal in the device

A pulse frequency high-speed differentiator is introduced, formed by two frequency dividers 4, 5, code entry gates 11, 12, switching element 13 and frequency subtraction unit 14. The control block 17 controls the operation of the device so that, after the "r-th multiplication cycle, in the memory of frequency dividers 3 and 5, the code of the" r-th period Lt; is entered. Respectively, in the next "g + + 1 multiplier cycle, the" i + 1 period code will be stored in the memory of frequency dividers 4 and 5. Due to this control, the output of frequency dividers 3 and 4 will always generate frequencies lagging behind one another for the previous period frequencies. So

after the "th cycle, the output of frequency divider 3 will change the frequency and will correspond to expression (3), and the output of frequency divider 4 will remain the same frequency, corresponding to the if-b period and equal to

F (t, .i) - t,). K-1, (h - r,). (four)

The pulses from the outputs of frequency dividers 3 and 4 are fed through the switching element 13 to the inputs of the frequency subtraction unit.

Claims (2)

The switching element 13 is controlled from block 17 in such a way that at the time of arrival of the next input frequency pulse, the outputs of block 13 are switched, swapped, so that one of its outputs will always have a leading signal in time. Frequency pulses are applied to the input of the frequency subtraction unit 13 which are delayed relative to each other by the value of the input frequency period. As it is known, when subtracting from the original signal Fx (ti) of the delayed Fx {ti-Ti), a frequency is obtained that is proportional to the first output signal of the original signal and the delay time: AF (ti) F ((- F, (ti - Tt) F; (tf) TI + + F: (T,) - n + ... F:, ((i) .Ti + +, (, where R-cvMAia are rejected members of the Taylor family, representing a methodical error and tendency to c to zero with decreasing delay time and small values of higher derivatives at these intervals. To get a frequency that does not depend on the period of change of the input frequency, the output frequency of the frequency subtraction unit is divided in the divider frequency 5 to a code proportional to the "r-th period. Pulses with a frequency Fx (ti) are sent to the pulse input of frequency divider 5, the memory of which contains the code from summing counter 9. At the output of frequency divider 5, pulses are generated that follow With frequency. (.).), Ttu about, i.e., proportional only to the derivative of the input signal. Pulses with frequency Fy (ti from the output of frequency divider 5 are fed to the input of the integrator counter of frequency multiplier 15, to the input of the counter-divider which receives pulses with frequency / o s Generator (. The frequency multiplier performs the role of the frequency integrator and is triggered by a control signal from the control unit. At the output of the frequency multiplier, a frequency t p is generated. (ii} ff y (/) () (About where t is the time, varying from ti to i + i. Thus, at the output of the frequency multiplier, a frequency is formed that changes linearly in time with a coefficient equal to the first frequency differential i.e. a frequency is proportional to the derivative of the amplified frequency at the time.The inputs of the frequency summing unit receive PULSES from the output of the frequency multiplier with frequency fz (fi, from the output of switching element 13 with frequency Fx (ti) and from the output of block 14 frequency subtraction divided by two in trigger 18 with a countable input ohm, with frequency (ti). The frequency summing unit controls the sign signal sign /.,;(/,) from the output of the frequency subtraction unit, which characterizes the sign of the increment of the multiplied frequency and the derivative of the input signal. Depending on this sign to the frequency Px (ti} are added or frequencies (ti) are subtracted from it.) A frequency summation block can be built on frequency subtraction blocks according to the number of input signals with intermediate frequency input. Then it is easily rearranged from summation to subtraction of frequencies. The frequency at the output of the summation block for the current "t + 1th period will be equal to / in" (Ti, i) K) ± ± /; (/) -. The invention The multiplier for the multiplication frequency of pulses, containing a reference frequency generator, a control unit, two frequency dividers, each of which consists of a subtracting counter and a memory register, connected through a code gate, whose control input is connected to the output of the subtracting counter, c summing a counter whose code output is connected via the code transfer valve to the installation input of the memory register of the first frequency divider, while the output of the reference frequency generator is connected to the input of the calculator The first counter of the frequency divider directly, and to the counting input of the summing counter through a second frequency divider, the setup input of which is connected to the input source terminal, characterized in that, in order to improve the speed and accuracy of the device, two additional frequency dividers are introduced into it , a switching element, a subtraction unit, a frequency multiplier, a frequency summation unit, a trigger and additional code transfer gates, the output of the first frequency divider and the OUTPUT of the first an additional frequency divider is connected via the switching element to the inputs of the frequency subtraction unit, the output of which is connected via a trigger to the first frequency addition input and through the second additional frequency divider to the first input of a frequency multiplier whose output is connected to the second input of the frequency addition unit whose third input is connected to the output of the switching element, the control input-with the sign output of the block of subtracted frequencies, and the output is the output of the device, while the generator output is often s connected to the pulse input of the first additional delkte; frequencies and to the second input of the frequency multiplier, and the set inputs of the do-iol Ittel frequencies and frequencies are connected to the code output of the sum of the Mounting counter in the following way: 4 add code or transfer code, which controls the inputs of which are connected to the single outputs of the block: control, other outputs of which have inputs connected to the single outputs of the unit; to the input inputs of the frequency multiplier and the switching element, to the fault inputs of the summing counter and memory registers of the first and two dololitelnyh frequency dividers. 5 Sources of information taken into account in the examination; 1.Avt. St. 354546, cl. N OZK 5/00, 1972. 2. Avt. St. No. 357668, cl. H OZK 5/01, 1973 (prototype). 0