SU372681A1 - G "" CHSSESIOZNAIAI - Google Patents

Description

one

The invention relates to a measurement technique and can be applied while simultaneously measuring the frequency and the azal shift of the low frequency signals.

The following digital frequency meters are known, in which the following balancing is performed by the difference of the periods of the measured and compensating signals.

A disadvantage of the known devices is that they do not provide simultaneous measurement of the frequency of the signal under study and its phase shift.

The invention eliminates this disadvantage due to the fact that in the proposed device an additional register and a trigger are used, one input of which is connected to the input terminal, the other to the output of the reference frequency generator, and the output to the installation input of the additional register, and the inputs of the latter counter second binary multiplier.

The drawing shows a block diagram of the proposed frequency meter-phase meter, which contains a reference frequency generator 1, two binary multipliers 2 and 3, consisting of a control counter 4, common to both multipliers, keys 5 and counters 5, 7, register 8, keys 9 and 10, the period comparison diagram // and trigger 12.

At the input 13 of the period comparison circuit 11, pulses arrive, the frequency and phase shift of which must be measured. The phase shift is measured relative to the single signal

entering the input 14.

With the arrival of the next pulse at the input 13, the period comparison circuit generates signals that close the keys 9 and 10 and set the binary counter 7

multiplier 3 in the "zero position. The input of counter 7 continuously receives pulses from the output of binary multiplier 2. With the arrival of the reference signal at input 14, a trigger 12. triggers. After a time not exceeding the period of the signal at the output of the reference frequency generator, trigger 12 returns to its original position. Upon the return of this trigger to its initial position, an impulse is formed at its output, with the help of which the code is copied from counter 7 to register 5.

By setting the counter 7 to the "zero" position on the pulse of the measured signal, the phase input of the periods is also reached.

measured by Ti and compensating G, - signals.

If, then the period comparison circuit 11 generates a signal that opens the key 9 for a time equal to the difference of these time intervals, and pulses from the output

binary multiplier 3 through key 9 and fed to the subtracting input of control counter 4.

If Ti.Ti-.t, then the comparison circuit 11 generates another signal, which opens the key 10 for a time equal to the difference of these time intervals, and the pulses from the output of the binary multiplier 3 through the key 10 arrive at the summing input of the control counter 4.

If Ti Ti-i, then the again pinching pulse of the measured signal through the comparison circuit 11 again closes the keys 9 and / (and, therefore, the code in control counter 4 does not change.

The code in counter 4 during a time equal to the difference in time intervals Ti and Gy-s changes in such a way that its new value n (Ti) becomes proportional to the frequency F.i of the measured signal. At the same time, the code rewritten from counter 7 to register 8 is proportional to the phase shift of the measured signal d-a relative to the reference.

An overflow pulse at the output of counter 7 appears after a time equal to the time of the previous period of the measured signal, i.e., the values of the existing and present periods of the measured signal are compared in each measurement. With the arrival of the next pulse of the measured signal, the cycle of operation of the device is repeated.

Thus, after each of the pulses of the measured signal that are stuck to the input in control counter 4, a code of a number proportional to the instantaneous phase shift of the measured signal relative to the reference signal is formed.

Subject invention

The following digital frequency meter-phase meter, containing two binary multipliers connected to a control counter, a reference frequency generator connected to one binary multiplier, and keys, outputs connected to the control counter, the first inputs to the period comparison circuit, and the second to the output of another

binary multiplier, characterized in that, in order to expand the possibilities of application, it contains an additional register and trigger, one input of which is connected to the input terminal, the other to the output

the generator of the reference frequency, and the output - with the installation input of an additional register, and the inputs of the latter are connected to the outputs of the counter of the second binary multiplier.