SU512468A1 - Dividing device - Google Patents

Description

(54) DEVICE FOR FISSION

19 "Start the initial installation of the control trigger.

The operation of the device is as follows.

Before the start of the Computation cycle, the dividend is recorded in register 2, the dividend is written, memory register 4 and iB are divisor register 5 - divider, buffer register 12 is brought to the zero state.

The "on input 19" trigger signal sets the trigger 5 to such a state that the element "AND W is prepared to pass pulses from the input 13 of the device, and the element" AND 9 is closed to pass these pulses. The trigger 14 of the reverse is in the state, iKOTOipoe is in, it includes 5 cases in the register, the subtractive input and 12 in the buffer register, the summing input.

11 | pulses arriving at input 13, are transferred to. The deduction to the register is 5 times the dividend, and the sum to the buffer repistor is 12; PA v.hod element “And 10 and through the element“ OR 6 on the subtraction in the repister 2 cases of him.

After the block // detects; zero state of the register 5 divider, it issues a pulse, which opens the state of the trigger 14 (reverse, goes to the enable input of the compare block 5 (codes), goes to the input of the element And 16.

After this point, the register 5 divider starts to work on the summation, the buffer repistr 12 - to subtract.

Blo; s 5 sravbni pro: izvodit comparison of the codes of the register 4 memory (de titel) and register 2 divisible. The comparison block 3 outputs the output signal only if the number in the memory reporter 4 is greater than the number in the register 2 of the dividend and the pulse output is present at the // block.

Otherwise, on its output, the jfie signal appears, i.e., until the package has an integer part of the quotient determined, block 5 of the comparison does not work.

The input of the counter 18 of the whole result through the element “And 16 will receive a pulse, because the second INPUT of this element“ And receives the enabling signal from the output of the control trigger 8; The prohibitory signal of the specified trigger locks the element "And / 5. Thus, the dividend is reduced by the divisor value. Then, as the pulses arrive and the logical input, it detects zeroing of the buffer register 12. The pulse from the output of the block ka // repeats the path already described, after which the dividend in register 2 ALARM will decrease by the value of the divider.

This process will continue as many times as the entire divider is laid down in the dividend. This number will determine the integer part of the quotient.

When the number in register 2 is delivered. For the first time it will turn out (less than the number in 1 register 4 memory, and when the output is block 11, the next | Impulse, comparison block 3 produces a pulse that changes the state of the trigger

8 control, after which the element "And 10 and the element" And 16 are closed for the passage of pulses, and the element "And 9 and the element" And 15 are prepared to pass the corresponding

signals.

Now the pulses from the input 13 of the device through the element "And 9 are fed to the input of the divider 7, therefore the pulses are received to the input of the register 2 of the dividend, the frequency of which is K times

less than the frequency and. M1 pulses at the input 13 of the device. At the inputs of the register 5 of the divider, the buffer register 12, the frequency of the pulses remains unchanged.

Further, the process continues in the same manner as described above, except that the pulses from the output of the block // through the element arrive at the input of the counter 17 of the fractional result. The division process will continue until it works.

block 1 of the zero-zero state of the register of the dividend.

Consider, iKaiKoe, number 0: it appears in the counter of a fractional result after the end of the division.

The time 3 for which the counter / 7 will be filled with pulses is different:

(I)

t K is

where / is the time of filling the counter / 7;

L is the division factor of the divider 7; .V - divisible (the number recorded in the register of dividend 2); / Uz - the whole part of the private, recorded

in the counter 18; fv - period after: dova: no impulses

device input 13.

During this time, at the input of the counter 17, the number of pulses per

)

   / .m

/ i-l d

 Rv; t

,,)

(N) n,

where Ld is the divisor (the number recorded in registers 4, 5).

From Formula II it is SEEED that by increasing the DO it is possible to achieve any necessary particular accuracy.

PRI m. Let dividend 20, divisor 6; nego.mo to get the quotient with an accuracy of two characters after the comma. - Choose K 100.

After starting the device, on input 1 19, “SinycK” at the output of logical power 11, three pulses are received, which through the open element “AND 16 arrive at the counter / 8 of the whole result.

After the appearance of the third pulse, the comparison unit 3 gives out a signal, because by this time: in register 2 of the dividend the number 2 is written, and 3 in memory register 4 is the number b; trigger 8 changes its state.

; In accordance with the formula II of the C4etch.l / 7 fractional result will go "other h :: layer of pulses, namely:

100 (20-18)

: 00

6

Thus, the quotient is determined as the readings of both counters separated by a comma, namely, 3.33.

During this time, 33x6 198 pulses will go through the input of the device, i.e. after receiving two more pulses, 1 which no longer affect the result, the block / registers the zero state of register 2 and generates a signal at the end of the division;

By asking 1000, you can get three 3) On, after that room, etc.

Claims (1)

Invention Formula The device for dividing, containing the counter of the whole result, the elements "AND," OR, the register of the dividend, the first output of which is connected to the block. You see the zero state of the reparator of the dividend; and the trigger of the connectors connection; with the first inputs of the buffer register and the first input the divider register, the second input of which is connected to the input of the device and to the second input of the buffer register, the output of which is connected to the corresponding input of the zero state register of the divider register and the buffer register, characterized by that. that, in order to increase the accuracy of the device, a fractional result counter, a divider, a control trigger, a register are entered into it memory and blcx srazienl, the first input of which is connected to the memory register, the second input is connected to the input of the reverse trigger and to the first inputs of the first and second element "And the outputs of which are respectively connected ico counters fractional and integer results, the second inputs of the first and second elemen. "And connected to the first and second outputs of the control trigger and the first inputs of the third and fourth elements" And, the second inputs of which are connected to the input of the device, the output of the third element " And connected to the input of the divider, the output of which is connected to the first input; . of the element “OR, whose second input is connected to the output of the fourth element“ AND, the output of which is connected to the input of the register of the dividend, the second output of which is connected to the third input of the comparison unit, the output of which is connected to the first input of the trigger, the second input which is connected to bus initial setup control trigger. / A-.