SU725238A1 - Pulse repetition frequency divider with fractional division coefficient - Google Patents

Description

(54) THE DIVIDER OF THE FREQUENCY RATING OF PULSES WITH A VARIABLE DIVISION COEFFICIENT

The invention relates to a pulse technique and can be used in discrete systems of automatic control, in measuring devices of nuclear electronics, as well as in pulse selection circuits.

A periodic pulse frequency divider is known, comprising a scaling circuit, gates, a trigger, a random number generator, and a code comparison unit. one .

The disadvantage of this device is low reliability

 The closest to the technical essence of the invention is a frequency divider with a variable variable division factor, containing in each fractional discharge a controlled divider, the output of which is connected to the single higher-case trigger input of the next highest fractional fraction, the second input of the second valve is connected to the input -controlled the divider of its bit, the output of the scaling circuit - with the input of the scaling circuit of the next higher fractional bit through the OR element, the output of the controlled divider with the single trigger input is less than first fractional bit first

input vent of the controlled divisor of integers - with a single output of an additional trigger, the zero input of which is connected: with the output of the scaling circuit of a higher fractional bit, and the unit input with an input bus and the second input of the valve at the input of the controlled divider of 2.

The disadvantage of this device is its complexity and, as a result, reliability is low.

The purpose of the invention is to increase the reliability of the device.

The goal is achieved by introducing an inverter, a numeric decoder, and a pulse shaper, the output of which is connected to the input of the zero divider unit of the integer part, in a variable pulse frequency divider with a variable division factor containing the integer part divider, OR elements, trigger and fractional part divider. and the input divider of the fractional part, and the inputs - with the outputs of the elements OR,

5 the first input of the first of which is connected to the output of the divider of the whole part and the first arc the input of the second element OR, the second through the inverter with the input of the device and the input of the divider whole

Claims (2)

725238: part three - with a direct trigger output, the inverse output of which is connected to the secondary input of the second element or, and the single and zero inputs - respectively to the output of the zero decider and the first output of the fractional splitter, the second output of which is connected to the input of the zero decoder, On The drawing shows a structural electrical circuit of a pulse frequency splitter. It contains a divider 1 integer part, an inverter 2, trigger 3, a divider 4 fractional parts, a decoder 5 zero, the first element b OR, the second element 7 OR, or 8 pulses 8, The operation of this device is considered on the example of a pulse frequency divider with a factor division 24.5. The switch divider 1 is set to obtain the coefficient 24, the switch divider 4 to the position 5 the initial state of the dividers 1.4 is zero). In this case, element 7 is closed with a inhibit signal from trigger 3, and element 6 from trigger 3 receives an enable signal. After 24 pulses have arrived at the input of divider 1, a resolution signal is received from its output to the input of element b. But from the output of the element b, the pulse does not follow, since there is no resolution from inverter 2. With the arrival on. enter the divider 1 and the inverter 2 of the 25th pulse, from the output of the element b to the shaper 8, a pulse arrives, which brings the divider 1 to the initial state, and the divider 4 records one pulse. In this case, the division factor of the divider is 25. After divisor 4 writes down five. pulses (after five divisions) with the signal from the first output of this division: the state of trigger 3; element b is closed, and the element with the inverse output of trigger 3 receives an enable signal. In this case, an impulse arrives at the input of the PF1 Transducer 8 through element 7 after the post is fed to the input of the splitter 1 of the 24th pulse. Consequently, the remaining five division cycles from ten occur with a division factor of 24, -: ---: After divider 4 has been calculated to the initial state by a signal from the decoder 5, trigger 3 is switched to the initial state and the division cycle begins first. These processes are repeated. Meanwhile, the average coefficient for green is 24.5. The device offered by the device is characterized by simplicity of circuit construction, it has increased reliability in operation at all possible numerical values of the division factor. The ability of the device to automatically change the division ratio enhances its functionality. The proposed divider can be used for the selection of pulses of duration, for example, in measuring devices of nuclear radio electronics. This advantage is realized as follows. When the length of the input pulses is greater than the literity of the puller 8, the divider 1 has time to additionally record one pulse after it has been reset to the initial state by a signal from the former 8. In this case, the division factor is automatically set equal to only the whole part of the division factor. The formula of the pulse frequency divider with a variable division factor containing an integer part divider, OR elements, a trigger and a fractional part divider, characterized in that, in order to improve reliability, an inverter, a zero decoder and a pulse shaper, whose output} connected to the installation input of the zero splitter of the integer part and the splitter input of the fractional part, and the inputs to the outputs of the OR elements, the first input of which is connected to the output of the splitter of the integer part and the second input of the second element OR, the second through the inverter with the input of the device and the input of the divider of the whole part, the third with the direct output of the trigger, the veggie output of which is connected to the second input of the second element OR, the unit and zero inputs respectively with the output of the zero decoder and the first output of the splitter fractional parts, the second output of which is connected to the input of the decoder zero. Sources of information taken into account in the examination 1. The author's testimony of the USSR No. 532964, cl. And 03 K 23/02, 04.05.75. 2. Authors certificate of the USSR 506130, cl. And 03 K 23/00, 01/17/74.