SU515289A1 - Pulse frequency divider - Google Patents

Description

(54) PULSE FREQUENCY DIVIDER

one

The invention relates to a pulse technique and can be used in the construction of digital computers nodes, telemechanics and information output devices.

It is known a device for dividing a part of pulses, built on counters with mutual reset, in which when one of the counting circuits overflows, one of the impulse® is emitted and the readings of the second counting are simultaneously reset.

schemes C.

The known pulse frequency divider contains two trigger counters, the counting inputs of which are combined and connected to the source terminal of the input pulse 2.

The aim of the invention is to improve the reliability of the device.

To do this, the OR element is entered into the divider, the first input of which is given a zero setting signal, the second input is connected to the zero output of the second trigger counter, and the output is connected to the installation input of the first trigger counter, the single input of which is connected to the installation input of the current trigger counter.

The drawing shows a structural electrical circuit of the pulse frequency divider.

The device consists of two trigger counters 1 and 2, performed on potential elements that implement the operation of Schaeffer NAND, one element OR 3, and terminal 4 of the source of input pulses.

The trigger counter 1 is expediently used without feedback with the maximum possible division factor. For proper operation of the device, the division ratio of the trigger counter 2 must be less than the division ratio of the trigger counter 1,

Pulse frequency divider works in a manner.

At the initial moment, all bits of trigger meter 1 are set to state O, at the input of the higher bit daurueno O, the output is level I. Trigger point counter 2 is set to O by the active level O from the output Q high order trigger points of counter 1 and is blocked. Thus, trigger- ing counter 2 will not respond to input pulses, and trigger counter 1 is ready for counting. With the arrival of the ij-hundredth pulse (If: K. / 2 where K, is the division ratio of the trigger counter 1). The highest bit of the trigger counter 1 will take state 1, thereby triggering the trigger counter 2; (I 12 - 1 pulse (K / De K - division factor of the trigger meter 2) will transfer the high bit of the trigger meter 2 to the state, at the output of the element OR 3, fuc-riroi iu level O, all bits of the trigger meter 1 set to the state O and the trigger counter 2 is blocked again. The device is prepared for a new cycle of operation. Since LO 1., then during the i, -th pulse up to (1. + time from t) -shgo at the input O the older discharge trigger meter 1. state 1 is stored.

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Claims (2)

“2 .4 Thus, the ratio of the pulse duration and the pause at the output of the trigger counter 1 is determined by the ratio of the division factors K and K-. Claims of the invention A pulse frequency divider containing two trigger counters, the counting inputs of which are combined and connected to the terminal of the source of the driving pulses, which are connected to the terminal. so that, in order to increase the reliability of the device, an OR element is inputted to the first input, the first input of which is given a zero setting signal, the second input is connected to the zero output of the second trigger counter, and the output to the installation input of the first trigger counter, single input which is connected to the installation input of the second trigger counter. Sources of information taken into account during the examination: 1.E. M. Martynov Synchronization in Discrete Communication Systems, M., Svz, 1972, p. 121. 2. Avt. St. No. 197278, M. class. NOZ k 23 / O4, dated 1968