SU1422404A1 - Pulse counter - Google Patents

Abstract

The invention relates to the field of automation and computer technology and can be used in devices for discrete information processing. The purpose of the invention is to obtain a noise-resistant sweep while maintaining the high speed of the counter. The counter and pulses contains an adder, elements of RSHI and cascades, each of which includes k bits. Each of the k bits consists of a trigger and an AND element, and the cascades from the first to (k-1) -th and the OR element. In order to achieve this goal, an element I is introduced into each cascade from the second to the k-th digit. Tables 1, 1, ill. (L

Description

The invention relates to automation and computer technology and can be used in discrete information processing devices, in particular as counters, pulse distributors and information coding devices with improved speed and the ability to detect errors.

The aim of the invention is to obtain a robust subtraction while maintaining high speed. due to the introduction of new design features.

The drawing shows a five-bit counter with a control number k 3, which has an increased speed and the ability of an error-proof pulse subtraction.

The meter contains summator 1, input bus 2, output blocks 3.1-345, error signal bus 4, elements; OR 5.1-5.3, cascades 6.1-6.3, triggers 7.1-7.3 of the cascade, first elements, AND 8.1-8.3 of the cascade, elements OR 9.1-9.2 cascade and the second elements AND 10.1-10.3 cascade.

The input bus 2 is connected to the inputs of the first AND of the elements AND .3 of all cascades 6.1-6.3. The inputs of the element OR 5.1 are connected to the direct outputs of the trigger 7.2 of the cascade 6.1 and the trigger

7.1 cascade 6 .. 2, element inputs OR

5.2 connected to the direct outputs of the flip-flops 7.3, 7.2 and 7 .1, respectively, of the cascades 6.1–6.3, the inputs of the OR 5.3 element are connected to the direct outputs of the flip-flops 7.3 and 7.2, respectively, of the cascades 6.2 and 6.3, the direct output of the the trigger trigger 7.1 of the cascade 6.1, the inputs of the elements OR 5.1-5.3, and the direct output of the trigger 7.3 of the cascade 6.3 are connected respectively to the default pins 3.1-3.5 and to the inputs of the adder 1, the output of which is connected to the bus 4, in each of the cascades 6.1 -6.3 inverse; trigger inputs 7.1-7.3 are connected respectively to the first inputs of the AND 10.1-10.3 elements, the second inputs of the AND 10.1-10.3 elements kada 6.3 are connected respectively to the outputs of the elements of AND 10.1-10.3 of the cascade 6.2, the second inputs of the elements of AND 10.1-10.3 of which are connected to the outputs of the elements

And 10.1-10.3 of the cascade 6.1, in each of the cascades 6.1-6.3, the direct codes of the trigger 7.1-7.3 are connected respectively to the second inputs of the AND 8.1 elements

Jq

15

20

25

thirty

Q

five

five

five

8.3, the outputs of which are connected respectively to the installation inputs of zero-trigger 7.1-7.3, additional inputs of elements AND 8.2 and 8.3 are connected respectively to the codes of elements AND 10.1 and 10-.2, the installation inputs to the unit of trigger 7.1 and 7.2 are connected respectively to the outputs of the elements OR 9.l and 9.2, the inputs of the OR element 9.1 of the cascade 6.1 are connected to the outputs of the elements AND 8.1-8.3 of the cascade .6.2, the inputs of the OR element 6.2 of the cascade 6.1 are connected to the outputs of the elements 8.2 and 8.3 of the cascade 6.2, in which the inputs of the OR 9.1 element connected to the outputs of elements AND 8.1-8.3 of the cascade 6.3, in the cascade .6.2, the inputs of the element OR 9.2 are connected to the outputs of the elements 8.2 and 8.3 of the cascade 6.3, the inputs of the installation in unit of trigger 7.3 of the cascades 6.1-6.3 are connected respectively to the outputs of the electrodes AND 8.3 of the cascades 6.2 6.3 and element 10.3 of the cascade 6.3, in which the output of the element 10.3 is connected to the inputs of the elements OR 9.1 and 9.2, and the third input of the element 10.3 is connected to the input bus 2.

The introduced elements and new connections ensure the operation of the counter in the subtraction mode by sequential search in the same bits of all cascades, starting with the low bit, the single bit, resetting it to the zero state and simultaneously setting it to the single state of the same name and the lowest bit. Dov previous cascade.

Ensuring noise immunity in the subtraction mode is achieved due to the presence of an adder at the output of the pulse counter, which makes it possible to continuously calculate the unit bits in the code combinations of the counter and in case of exceeding the number of units of a given value k, an error signal occurs. ..with

The work of the proposed counter will be considered on a concrete example with the number of bits of the counter n 5 and with the control number k 3.

The code combinations of the state of the pulse counter and stages are listed in the table.

As can be seen from the table, in the same-bit bits of all cascades, there can be no more than one unit. When moving from one combination of the counter to another, a unit transition occurs.

ten

the lowermost bit of any cascade, to zero and at the same time the zero transition in the same discharge of the previous cascade to one, for example, the transition from combination No. 1 to combination No. 2. If the younger unit is not in the first discharge, then a simultaneous transition occurs per unit of all lower order bits of the previous cascade.

The counter works in the following way.

In the initial state in the cascades 6.1-6.2 there are code combinations 15 000, and in the cascade 6.3-111. Accordingly, on the output buses 3.1-3.5, the code combination 11100 is found. With the arrival of the first clock pulse on the input bus 2, the 20 trigger 7.1 of the cascade 6.3 is reset via the first element 8.1 of the same cascade. At the same time, this signal through the OR element 9.1 of the cascade 6.2 sets the trigger 7.1 of the same cascade to one state. As a result, the second stage will have a combination of 001, in the third - 110, and on the output tires 3.1-3.5 - 11010. The next clock signal is received through element 8.1 of the cascade 6 2 to the input of the R-trigger 7..1 of the same cascade, drops it at

the zero state and at a time through the OR element 9.1 of the cascade 6.1 sets the trigger of 7.1 of the same cascade to one state. In the first stage, 001 is obtained, in the second, obo, in the third - 110, and at the output of the counter - 11001. With the arrival of the next clock pulse,

reset of trigger 7.1 of cascade 6.1 to the zero state. The output of the counter is 11000. The next clock pulse resets the trigger 7.2 of the cascade 6.3 to the zero state and simultaneously through the elements of IL 9 ,. 1-9.2 of the cascade 6.2 sets in one state the triggers 7.1-7.2 of the same cascade. In cascade 6.1 there will be 000, in cascade 6.2 - 011, in cascade 6.3 - 100. At the output of the counter - 10110 and so on. Upon receipt of a clock pulse

25

thirty

35

40

4g

50

Then, at 10000, the trigger 7.3 of the cascade 6.3 is reset to the zero state and, at the same time, the trigger through the elements OR 9.1-9.2 of the trigger 7.1-7.3 of the cascade 6.2 is set to one. As a result, in the cascade 6.1 0

50

000, in the cascade 6.2 - 111, in the cascade 6.3 - 000, and at the output of the counter - 01110 and so on. When the counter is zeroed, when the outputs of the combination are 00000, and in all stages there are also zero combinations of 000, with the arrival of the clock pulse from the input bus 2 to the third input of the second element AND 10.3 of the cascade 6.3, the trigger of 7.1-7.3 of the cascade 6.3 is installed through elements OR 9.1-9.2 of this cascade. As a result, in the 6.3 cascade there will be a combination of 111, in the cascade of 6.2 - 000, in the cascade of 6.1 - 000, and on the output of the meter buses 3.1-3.5 - 11100, i.e. the counter goes to the initial state.

In the event that the pulse pattern of the code combination with the number of unit bits greater than k 3 appears on the output buses 3.1-3.5, the adder 1 generates an error signal 5, which is sent to WIiIiy 14 of the error signal.

Claims (1)

Formula of Invention The counter has pulses containing 0 input bus, adder, n output buses, a group of p-2 elements OR and n-k + 1: cascades, where k is a control number, less than the number n, but more than zero, each of the cascades contains k bits each of which contains the trigger, the first element And, the first bit contains the second element And the bits from the first to (k-1) -th contain the element OR, the inputs of the first elements And each bit are connected to the input bus, and the direct output of the trigger i-ro the bit of the j-ro cascade, where i 1, ..., k, j 1, ..., n-k + 1, is connected to the input (i + j-2) of the OR of groups of elements OR, the outputs of the elements OR of which are connected to the inputs of the adder and S.; the corresponding (p-2) output buses, the remaining buses are connected to the additional inputs of the adder and to the direct outputs of the first trigger and the last bits, respectively, of the first and last cascades, which is due to the fact that, for the purpose of robust subtraction, a second element AND is inserted into each cascade from the second to the k-th digit, in each stage in each bit inverse trigger output connected to, first the input of the second element And, the second input of which is connected to the output of the second element AND of the same discharge of the previous cascade, in each stage in each discharge the direct output of the trigger is connected to the second input of the first element And, the output of which is connected to the input of the zero setting of the trigger, the auxiliary input of the first element And in the bit, starting from the second, is connected to the output of the second element AND the previous bit, in each stage in each bit, except the senior one, the input of the unit to the trigger unit is connected to the output of the OR element, the input which in cascades, except the older one, are connected to the outputs of the first elements of the same and older bits of the subsequent cascade, the input of the installation in 1 senior trigger of all the cascades, except the older one, is connected to the output of the first element And the older bit of the subsequent cascade, in the older cascade the output of the second element AND of the higher order is connected to the inputs of the elements OR of the lower order bits and with the input of the installation in 1 trigger of the higher bit; f 11010 10010 11001 10 10,000 1000 11,01110 10110 12,01101 10101 13 01100 3 1 16 2 3 1 17  2 000 01000 000 1 100,000 00111 3 1 18 2 3 1 19 2 3 1 20 2 3 000 000 00110 000 000 000 000 000 000 2 3 111 1 2 3 110 1 2 3 00100 100 1 2 3 00000 000 1 2 3 Table continuation