SU1383490A1 - Combined counter - Google Patents

Abstract

The invention relates to computing and can be used in counting devices, producing sh. Their counting in binary code and in the Gre code. The purpose of the invention is to increase the reliability of operation. To do this, in all bits of a binary counter with internal transfer formation and borrowing, except for the last one, additional RS-flip-flops are introduced, the inputs of which are connected to the outputs of the discharge loan and to the outputs of the binary account of the next discharge. 2 ill., 1 tab.

Description

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The invention relates to binary pulse counters and provides binary and Gre code counts with increased reliability of operation.

The aim of the invention is to increase the reliability of the operation.

FIG. 1 shows a block diagram of a combined meter; in fig. 2 is a schematic diagram of a counting trigger.

The combined counter contains bits on counting triggers 1-3 and RS triggers on AND-OR-NOT 4-7 elements in all bits except the last.

The counting trigger is made (Fig. 2) according to the scheme of three triggers on the AND-NE 8-13 elements with internal transfer and borrowing, outputs 14 and 15 of the main trigger of each of the counting triggers 1-3 are connected to the output buses of the binary counting, and for the latter bit and counting buses in the Gre code, the transfer output of the counting trigger of the nth digit is connected to the counting input of the (n + 1) -th bit, each of the additional RS flip-flops is formed by the first and second elements AND-OR-NOT, the outputs of which are connected to the account tires in the Gre code and, accordingly, with the first in The inputs of both groups of inputs of the second and first elements are AND-OR-NOT, the second inputs of the first groups of inputs are interconnected and connected to the output of the counting trigger of this bit, and the second inputs of the second groups of inputs of the first and second elements are connected respectively to the direct and inverse binary code of the next bit.

The combined meter works in the following way.

The state of the inputs and outputs of the elements of its components in the process of work are summarized in a table.

Counting pulses are fed to the input 16 of the combined counter.

Let the initial level at the input 16 of the counter is set to a logical level “O (line 1 of the table). In this state, the binary counter Qs. Q2, Qi is 000, and the state of the counter in the Gre Qs code, Q, Qs is 001. The first counting pulse (line 2 of the table) switches the trigger (Qi, Qi) to the state Q: 1, which changes the state exit 17 from “Oh to“ 1.

As a result, the state of the binary counter Qa, Q2, QI becomes equal to 001.

Resetting the counting pulse (3- row tab.) First causes switching of output 18, and then switching of output 19 from state “1 to state” O, which leads to

switching the trigger (Q4, Q4) to the state Q4 1. The receipt of the next. the counting pulse to input 16 (4- row of the table) causes the trigger (Qi, Qi) to switch to the state, which in turn causes a change in the state of output 18 from “0 to” 1. By this signal, the trigger (Qa, Q2) switches to the state Q2 1, which leads to a change in the state of output 19 from "O to" 1. As a result, the state of the binary counter Qs,

5 Q2. Qi will become equal to 010, and the state of the counter in the Gre Qa, Q4, Qs Oil code. Further operation of the circuit can be traced by viewing the successively listed state table of the inputs and outputs of the elements.

0 Analysis of the operation of the circuit shows that the proposed combined counter produces a binary code count (output states Qa, Q2, Qi) and in the Gray code (output states Qa, Q4, Qs) with an increased reliability of operation.

Claims (1)

Invention Formula The combined counter, each bit of which contains a symmetric counting trigger according to the scheme of three triggers on the AND – NE elements with internal transfer and borrowing, the main trigger outputs of each of the counting triggers are connected to the output buses of the binary counting, and for the last bit 5 with counting tires in the Gre code, the transfer output of the n-th digit counting trigger is connected to a (nfl) -ro digit count input, characterized in that, in order to increase the reliability of operation, additional bits are introduced in all bits except the last RS-triggers, each of which is formed by the first and second AND-OR-NOT elements, the outputs of which are connected to the counting buses in the Gre code and, respectively, with the first inputs of both groups 5 inputs of the second and first elements are AND-OR-NOT, the second inputs of the first groups of inputs are interconnected and connected to the output of the counting trigger trigger of a given bit, and the second inputs of the second groups of inputs of the first and second elements are connected 0, respectively, with the direct and inverse binary code of the next bit. F1lg, 1