RU2024193C1 - Analog-to-digital converter incorporating random error correction provision - Google Patents

Abstract

FIELD: data-processing and measurement technology. SUBSTANCE: analog-to-digital converter is provided in addition with one more single-bit digital-to-analog converter, driven square-pulse generator, NOT gate, binary counter, multiplexor, first and second AND gates, OR gate, RS flip-flop, first and second pulse shapers. EFFECT: improved noise immunity of analog-to-digital converter. 5 dwg

Description

 The invention relates to information-measuring equipment and is intended for converting an analog signal into a digital code by the method of bitwise balancing with high noise immunity.

 Known ADC, correcting random errors that occur during the measurement [1].

 Its disadvantage is the increase in conversion time due to the fact that the number of clock cycles per one measurement becomes variable, and to check the last bits of the ADC, it is necessary to introduce additional excess bits.

 An ADC is also known in which, to reduce the uncertainty of the threshold of the comparator, the Getty method (sliding scale) is implemented [2].

 In this converter, a greater number of transformations are used to achieve the required accuracy. This significantly increases the conversion time, which is a significant drawback of this method.

 In the ADC, the noise affects the process of converting the input signal U (I) to the output code, introducing a random error. In the bit-by-bit ADC, a random error arises due to the false operation of the comparison device and especially affects the conversion process at the moments of the determination of the least significant bits. The influence of random error can be reduced if statistical processing is applied, which consists in the fact that N results of the AD conversion are taken and their mathematical expectation is calculated. This method N times increases the conversion time of the ADC.

 The closest in technical essence (prototype) is an ADC containing the main digital-to-analog converter (DAC), a summing circuit, a comparing device, a register of successive approximations, a clock pulse generator, an additional DAC, an RS-trigger, an OR element, a register with unit transfer circuits. [3]. In this ADC, the dynamic error correction from the transient process that occurs when the compensating voltage of the upper bits of the main DAC is established is carried out. The ADC, in comparison with the known ones, provides higher performance, since the register is excluded from the chain of successive approximations, i.e. reduced the clock cycle of the ADC.

 The disadvantage of the ADC is the low noise immunity, as a result of which a random error is introduced into the result of the AD conversion.

 The aim of the invention is to increase the noise immunity of the ADC of bitwise balancing using the random error correction algorithm.

 The goal is achieved by the fact that in an ADC with random error correction, containing a series-connected main DAC, a summing unit, a comparing device, the second input of which is an input bus, a sequential approximation register, the clock input of which is connected to the output of a clock generator, an additional DAC whose output connected to the second input of the summing unit, trigger, OR element, delay element, controlled pulse generator, multiplexer, two AND elements, counter, one-shot, elem ent NOT, two pulse shapers, the outputs of which are connected to the first and second inputs of the OR element, the output of which is connected to the first input of the first AND element, the second input of which is combined with the first information input of the multiplexer and connected to the output of the comparison device, and the output is connected to the counting input a counter, the zero input of which is combined with the control input of the controlled pulse generator and is connected to the output of the one-shot, and the overflow output is connected to the second information input of the multiplexer, the control input of which is combined with the first input of the second And element and is connected to the trigger output, the R- and S-inputs of which are connected respectively to the “End of conversion” output and the high-order output of the group of the least significant bits of the register of successive approximations, the outputs of the group of the highest and lowest bits of which are output bus and connected to the corresponding inputs of the main DAC, with the second input of the second element And connected to the output of the clock generator, and the output to the input of a single vibrator, the output is controlled by the pulse generator is connected to the input of the first pulse shaper, through the delay element with the input of the additional DAC, and through the element NOT with the input of the second pulse shaper, while the output of the multiplexer is connected to the information input of the sequential approximation register.

 Comparison of known technical solutions with the declared ADC showed that its significant distinguishing features is the presence of a combination of new nodes and connections. New nodes: delay element, controlled pulse generator, multiplexer, two AND elements, counter, one-shot, NOT element, two pulse shapers. New functional connections: the outputs of two pulse shapers are connected to the first and second inputs of the OR element, the output of which is connected to the first input of the first AND element, the second input of which is combined with the first information input of the multiplexer and connected to the output of the comparison device, and the output is connected to the counting input of the counter , the input of which is set to zero, is combined with the control input of a controlled pulse generator and is connected to the output of a single-shot, and the overflow output is connected to the second information input m a duplexer, the control input of which is combined with the first input of the second AND element and is connected to the trigger output, the R- and S-inputs of which are connected respectively to the “End of conversion” output and the high-order output of the low order group of the successive approximation register, the high and low order group outputs which are the output bus and connected to the corresponding inputs of the main DAC, the second input of the second element And connected to the output of the clock generator, and the output to the input of the one-shot, output a controlled pulse generator is connected to the input of the first pulse shaper, through the delay element with the input of the additional DAC, and through the element NOT with the input of the second pulse shaper, while the output of the multiplexer is connected to the information input of the sequential approximation register.

 No technical solutions with similar distinctive features were found in the patent and scientific literature, therefore, the proposed ADC has significant differences and meets the novelty criterion.

 The introduction of new nodes and new functional relationships provides an increase in the ADC noise immunity due to the correction of a random error, which is carried out by means of the statistical processing of the compensating voltage carried out in the determination of each low order bit.

 In FIG. 1 shows a functional diagram of the proposed ADC, which contains the main DAC 1, the summing unit 2, the comparing device 3, the register 4 of successive approximations, the generator 5 clock pulses, the additional DAC 6, the RS-flip-flop 7, the element OR 8, the delay element 9, a controlled generator 10 pulses, multiplexer 11, the first 12 and second 13 elements And, the counter 14, one-shot 15, the element NOT 16, the first 17 and second 18 pulse shapers. The main DAC 1, the summing unit 2, the comparing device 3, the second input of which is the input bus, the sequential approximation register 4, the clock input of which is connected to the output of the clock generator 5, the additional DAC 6, the output of which is connected to the second input of the summing unit 2, RS trigger 7, element OR 8 connected in series. The outputs of the first 17 and second 18 pulse shapers are connected to the first and second inputs of the OR element 8, the output of which is connected to the first input of the first element And 12, the second input of which is combined with the first information input of the multiplexer 11 and connected to the input of the comparison device 3. The output of the element And 12 is connected to the counting input of the binary counter 14, the zero input of which is combined with the control input of the controlled rectangular pulse generator 10 and is connected to the output of the one-shot 15. The binary overflow output the counter 14 is connected to the second information input of the multiplexer 11, the control input of which is combined with the first input of the second element And 13 and connected to the output of the RS-flip-flop 7. The R- and S-inputs of the RS-flip-flop 7 are connected respectively to the output "Transformation end" and the output the highest category of the group of the least significant bits of the register of 4 successive approximations, the outputs of the group of the highest and lowest bits of which are the output bus and connected to the corresponding inputs of the main DAC 1. The second input of the second element And 13 is connected to the output of the generator 5 clock pulses, and the output is with the input of a single-shot 15. The output of the controlled pulse generator 10 is connected to the input of the first pulse shaper 17, through the delay element 9 with the input of the additional DAC 6, and through the element 16 with the input of the second pulse shaper 18. The output of the multiplexer 11 is connected to the information input of the register 4 successive approximations.

 The process of converting the input signal to the output code in the claimed ADC occurs in the same way as in the prototype. The difference is that during the balancing process, when determining each bit from the group of the least significant bits, statistical processing of logical signals from the output of the comparator 3 is carried out.

1-e

. (1)
Исходя из выражения (1) можно по- лучить время Т_уст, необходимое для установления переходного процесса с заданной приведенной погрешностью γ_прив:
Δ = U_макс- U_макс+ U_макс· e

;
Δ = U_макс· e

;
e

=

= γ_прив;
Т_уст = - τ ˙ ln γ_прив. (2)
Если учесть, что γ =

, то выражение (2) можно упростить следующим образом:
t = T_уст= -τ·ln

;
Т_уст = - τ ˙ ln2^-N;
T_уст = N ˙ τ ˙ln2 ≈ 0,69˙N ˙ τ, (3) где N - номер разряда АЦП, причем N = 1, является младшим разрядом, а N = 16 - старшим разрядом (для шестнадцатиразрядного АЦП); τ - постоянная времени переходного процесса в аналоговых узлах АЦП (с); γ_прив - приведенная погрешность; U_макс - максимальная амплитуда i-го разряда; Δ - абсолютная погрешность; t, Т_уст - время, необходимое для установления переходного процесса с заданной погрешностью.It is known that the time for establishing the higher bits is longer than the time for establishing the lower bits. The time of establishment of each discharge can be determined based on the permissible absolute error of the ADC and the weight of each discharge. The absolute error in establishing each category can be defined as
Δ = U _max - U

1st

. (1)
Based on the expression (1), we can obtain the time T _mouth necessary to establish a transient process with a given reduced error γ _priv :
Δ = U _max - U _max + U _max · e

;
Δ = U _max

;
e

=

= γ _priv ;
T _mouth = - τ ˙ ln γ _pref . (2)
Given that γ =

, then expression (2) can be simplified as follows:
t = T _mouth = -τ

;
T _mouth = - τ ˙ ln2 ^-N ;
T _mouth = N ˙ τ ˙ln2 ≈ 0.69˙N ˙ τ, (3) where N is the ADC bit number, with N = 1, is the least significant bit, and N = 16 is the most significant bit (for sixteen-bit ADC); τ is the time constant of the transient in the analog nodes of the ADC (s); γ _priv - reduced error; U _max - the maximum amplitude of the i-th discharge; Δ is the absolute error; t, T _mouth - the time required to establish a transition process with a given error.

Since the period of the clock pulses does not change, after the establishment of each bit from the group of the least significant bits, additional time remains
T _{add i} = T - T _{mouth i} , where T is the period of clock pulses; T _{mouth i} - the time required to establish the transition process of the i-th discharge with a given error (Fig. 2).

The extra time T _{add i is} used for statistical processing of the compensating voltage U _k by processing the logic signals from the output of the comparator 3. During T _{add i,} the compensating voltage U _(k) containing random noise is superimposed from the output of the additional single-bit DAC 6 via block 2 summing a rectangular signal with a weight equal to the weight of the least significant bit. At the same time, a sequence of logical “0” and “1” appears at the output of the comparator device, with the help of which it is possible to determine “above” or “below” the threshold of operation of the comparator 3, the average value of the compensating voltage U (k) with the superimposed noise is found, and therefore , the reliable value of the logical signal at the input of the register 4 consecutive approximations (Fig. 3).

 The process is as follows.

, (4) где К - число импульсов с выхода ждущего генератора 10 прямоугольных импульсов за время, равное
Т_упр = Т - Т_уст.
Компенсирующее напряжение U(к) вместе с наложенным прямоугольным сигналом в некоторые моменты времени больше или равно порогу срабатывания сравнивающего устройства 3, что вызывает его переключение из одного логического состояния в другое. Если при этом по каждому перепаду сигнала с выхода ждущего генератора 10 прямоугольных импульсов через равные промежутки времени фиксируется логический уровень на выходе сравнивающего устройства 3, то по характеру полученной за время действия управляющего сигнала Т_упр последовательности "0" и "1" можно сделать следующие выводы.When the senior bit is turned on from the group of lower digits of the register of 4 consecutive approximations, trigger 7 switches from "0" to "1". In this case, the multiplexer 11 disconnects the input of the register of 4 successive approximations from the output of the comparing device 3 and connects it to the output of the binary counter 14. After switching the trigger 7 from "0" to "1", the passage of clock pulses from the output of the generator 5 clock pulses through the element And 13 the input of the monostable 15. at the inverting output of monostable 15 to the positive differential clock pulse generated control signal _Ctrl T, whose duration is T = T _simp - T _mouth, where T - differential clock pulses T _mouth - the time of establishment of the senior level from the group of younger ones (Fig. 4). The control signal T _control includes a standby generator 10 of rectangular pulses and allows the binary counter 14. The compensating voltage U (k) is superimposed on a rectangular signal from the output of the additional DAC 6 with a weight equal to the weight of the least significant bit and frequency
F _GII0 =

, (4) where K is the number of pulses from the output of the waiting generator 10 rectangular pulses in a time equal to
T _control = T - T _mouth.
The compensating voltage U (k) together with the superimposed rectangular signal at some points in time is greater than or equal to the threshold of operation of the comparison device 3, which causes it to switch from one logical state to another. If at the same time for each difference in signal from the output of the waiting generator 10 rectangular pulses at regular intervals, a logic level is fixed at the output of the comparator 3, then by the nature of the sequence “0” and “1” obtained during the operation of the control signal T _control , we can draw the following conclusions .

(к) принимается больше порога срабатывания сравнивающего устройства 3 и в регистр 4 последовательных приближений записывается логическая "1".If the number of logical "1" at the output of the comparator 3 is greater than or equal to the number of logical "0", then the average value of the compensating voltage

(k) more than the threshold of the comparison device 3 is received and the logical "1" is written in the register 4 of successive approximations.

 If the number of logical "1" at the output of the comparing device 3 is less than the number of logical "0", then the logical "0" is written to the register 4 of successive approximations.

The binary counter 14 performs the function of comparing the number of logical “0” and “1”. It counts the number of logical “1” coming from the output of the comparing device 3 during the duration of the control signal T _control . For example, if the counter is binary four-digit and has outputs with a weight of 1-2-4-8, then at the output with a weight of "8" logical "1" appears only after nine pulses are received at the input of the counter (logical "1"). If less than nine logical “1s” are received, then the output of counter 14 is logical “0” and a logical “0” is written to the register of 4 successive approximations.

 The number of pulses of the superimposed rectangular signal coming from the output of the additional single-bit DAC 6 is half the conversion factor of the binary counter 14 and in this example is K = 8.

 Writing to the counter 14 is made on the positive and negative drops of the signal coming from the output of the waiting generator 10 rectangular pulses.

_, (5) где Z - логический сигнал на выходе сравнивающего устройства 3.As a result of the comparison, during the operation of the control signal T _control at the output of the comparing device 3, a logical signal Z is generated according to the rule
Z =

_, (5) where Z is the logic signal at the output of the comparator 3.

Величина Y есть не что иное, как в цифровой форме оценка математического ожидания установившегося значения компенсирующего напряжения U(к) за время действия управляющего сигнала Т_упр:
M[U(K)] = lim

U_j(K) (6)
Время Т_доп, необходимое для статистической обработки компенсирующего напряжения U(к), зависит от времени Т_су3 установления переходных процессов в сравнивающем устройстве 3 и от числа сравнений n, где n = 2К, К - число периодов наложенного прямоугольного сигнала с выхода дополнительного одноразрядного ЦАП 6:
Т_доп = Т_су3 ˙ n = Т_су3 ˙ 2 ˙ К (7)
Исходя из выражения (7), старшим разрядом из группы младших разрядов будет тот разряд, у которого время Т_{доп i} = Т - Т_{уст i} больше или равно времени Т_доп = К ˙ Т_су3, если время Т_{доп i} определяет, начиная от самого старшего разряда.The binary counter 14 captures the number of events Z = 1 at discrete time instants determined by the element And 12. After n comparisons are made, the output of the binary counter 14 causes a logical signal Y according to the rule
ϒ =

The value of Y is nothing more than a digital estimate of the mathematical expectation of the steady-state value of the compensating voltage U (k) during the duration of the control signal T _control :
M [U (K)] = lim

U _j (K) (6)
The time T _add necessary for the statistical processing of the compensating voltage U (k) depends on the time T _{su3 for the} establishment of transients in the comparison device 3 and the number of comparisons n, where n = 2K, K is the number of periods of the superimposed rectangular signal from the output of the additional single-bit DAC 6:
T _add = T _su3 ˙ n = T _su3 ˙ 2 ˙ K (7)
Based on the expression (7), the highest rank from the group of the least significant bits will be that category for which the time T _{add i} = T - T _{mouth i is} greater than or equal to the time T _add = K ˙ T _su3 , if the time T _{add i} determines, starting from the most senior level.

. (8)
К примеру, если в заявленном АЦП используется ЦАП К427ПН2 с временем установления Т_уст = 10 мкс и основной приведенной погрешностью γ_прив = 0,0015%, то из выражения (2) находят постоянную времени переходного процесса τ = 0,91 мкс. Отсюда из выражения (3)
Т_{уст 16} = 16˙0,69˙ τ = 10 мкс; Т_{уст 11} = 6,9 мкс;
Т_{уст 15} = 9,4 мкс; Т_{уст 10} = 6,3 мкс;
Т_{уст 14} = 8,7 мкс; Т_{уст 9} = 5,6 мкс;
Т_{уст 13} = 8,2 мкс; Т_{уст 8} = 5,0 мкс;
Т_{уст 12} = 7,5 мкс; Т_{уст 7} = 4,4 мкс;
Т_{уст 6} = 3,8 мкс; Т_{уст 3} = 1,9 мкс;
Т_{уст 5} = 3,1 мкс; Т_{уст 2} = 1,2 мкс;
Т_{уст 4} = 2,5 мкс; Т_{уст 1} = 0,6 мкс.The minimum number of superimposed rectangular pulse signal output from the K _m of additional 6-bit DAC can determine depending on from which a confidence level of P _rows is the average value of the offset voltage U (k):
K _min =

. (8)
For example, if the claimed ADC uses the K427PN2 DAC with the establishment time T _mouth = 10 μs and the main reduced error γ _priv = 0.0015%, then from the expression (2) find the transition time constant τ = 0.91 μs. Hence from the expression (3)
T _{mouth 16} = 16˙0.69˙ τ = 10 μs; T _{mouth 11} = 6.9 μs;
T _{mouth 15} = 9.4 μs; T _{mouth 10} = 6.3 μs;
T _{mouth 14} = 8.7 μs; T _{mouth 9} = 5.6 μs;
T _{mouth 13} = 8.2 μs; T _{mouth 8} = 5.0 μs;
T _{mouth 12} = 7.5 μs; T _{mouth 7} = 4.4 μs;
T _{mouth 6} = 3.8 μs; T _{mouth 3} = 1.9 μs;
T _{mouth 5} = 3.1 μs; T _{mouth 2} = 1.2 μs;
T _{mouth 4} = 2.5 μs; T _{mouth 1} = 0.6 μs.

If we take K521CA3 comparator as comparing device 3 with the settling time T _su3 = 200 ns, and the number of pulses of the superimposed rectangular signal from the output of the waiting generator 10 rectangular pulses is K = 16, then the time T _add required for the statistical processing of the compensating voltage U (k ), is determined from the expression (7):
T _add = 2˙K˙T _su3 = 2 ˙16˙0.2 μs = 6.4 μs.

The time T _{add i is} greater than T _add = 6.4 μs, starting from the fifth digit, which should be taken as the senior discharge from the group of the younger ones.

 A circuit for isolating time points during which a logic level is determined at the output of the comparing device 3 consists of an element 12, an element 8, an element 16, the first 17 and second 18 pulse shapers. The scheme works as follows. The pulses from the standby generator 10 rectangular pulses are fed to the input of the first driver 17 of the pulses, which generates a short pulse from the positive edge, and to the input of the second driver 18 of the pulses through the element HE 16, which, in turn, generates a short pulse from the negative edge of the output signal waiting generator 10 rectangular pulses. At the output of the OR element 8, the sum of the short pulses coming from the outputs of the first 17 and second 18 pulse shapers is selected, which determines the time moments during which the determination of the logical levels at the output of the comparing device 3 (Fig. 5) is performed.

 The delay element 9 is designed to delay the operation of an additional single-bit DAC 6 for the time necessary to highlight the time points during which the logic levels at the output of the comparing device are determined, and to write these logic levels to the binary counter 14.

Claims (1)

 ANALOG-DIGITAL CONVERTER WITH CORRECTION OF ACCIDENTAL ERROR, comprising a series-connected main digital-to-analog converter, a summing unit, a comparator, the second input of which is an input bus, a serial approximation register, the clock input of which is connected to the output of a clock pulse generator, an additional digital-to-digital with the second input of the summing unit, a trigger, an OR element, characterized in that a delay element is introduced into it, controlled pulse generator, multiplexer, two AND elements, counter, one-shot, NOT element, two pulse shapers whose outputs are connected to the first and second inputs of the OR element, the output of which is connected to the first input of the first AND element, the second input of which is combined with the first information input the multiplexer and is connected to the output of the comparing device, and the output is connected to the counting input of the counter, the input of which is set to “0” and connected to the control input of the controlled pulse generator and is connected to the output of one vibrator, and the overflow output is connected to the second information input of the multiplexer, the control input of which is combined with the first input of the second And element and is connected to the output of the trigger, the R- and S-inputs of which are connected respectively to the output "Transformation end" and the high-order output of the low order group register of successive approximations, the outputs of the group of high and low digits of which are the output bus and are connected to the corresponding inputs of the main digital-to-analog converter, the second input being of the And element is connected to the output of the clock generator, and the output is to the input of a single vibrator, the output of the controlled pulse generator is connected to the input of the first pulse shaper, through the delay element - to the input of an additional digital-to-analog converter, and through the element NOT - to the input of the second pulse shaper, when the output of the multiplexer is connected to the information input of the register of successive approximations.

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