RU2019030C1 - Voltage-to-code converter - Google Patents

Abstract

FIELD: digital information and measurement equipment. SUBSTANCE: voltage-to-code converter has analog storage, parallel and main analog-to-digital converters, digital-to-analog converter, clock pulse generator. Reference voltage fed to digital-to-analog converter is greater than reference voltage supplied to parallel analog-to-digital converter by value of its less significant digit. EFFECT: increased speed of response with growth of dynamic accuracy. 2 dwg

Description

 The invention relates to a digital information measuring technique and can be used to convert analog signals to digital code for interfacing digital computers with analog channels having a wide dynamic range of input signals.

 A known voltage-to-code converter based on the principle of bitwise balancing with separate determination of order and mantissa codes for each signal value, comprising a comparator, a control unit, a clock, a register, a reference voltage source, a decoder and a code-to-voltage converter, made in the form separate nodes corresponding to the order and mantissa of the numerical equivalent. However, it has a low conversion speed, since the order of the output code is determined sequentially, bit by bit.

 The closest in technical essence to the proposed device is an analog-to-digital converter containing a clock pulse generator, a control unit, a comparator, the direct input of which is connected to the input bus, and the inverse is connected to the reference voltage bus through series-connected digital-to-analog converters. In addition, the first and second AND elements, the NAND element, reversible and binary counters, the prohibition element, the key block and the NOT element, the input of which is connected to the output of the comparator and to the first inputs of the first and second elements of AND, are introduced into the analog-to-digital converter and the output is connected to the countdown input of the reverse counter, the direct counting input of which is connected to the output of the first element And, the clock input through the inhibit element is connected to the output of the clock pulse generator and the second input of the second element And, the reset input is connected to the output of the control unit, with the binary counter reset input, and the outputs are connected to the inputs of the first digital-to-analog converter, with the input of the key block, and the nth output is connected to the third input of the second AND element and the first input of the AND-NOT element, the fourth input of which is connected to the second input of the AND-NOT element and the second input of the control unit, the third output of which is connected to the second input of the inhibit element and to the control input of the key block. In this case, the output of the AND element is NOT connected to the second input of the first AND element, and the output of the second AND element is connected to the counting input of the binary counter, the outputs of which are connected to the inputs of the second digital-to-analog converter.

 The main disadvantages of the device, taken as a prototype, is that the known device at the stage of "Normalization", when the reference voltage is generated for the first digital-to-analog converter, works essentially as an analog-to-digital converter for serial counting, and at the stage of "Conversion" - as a follow-up analog-to-digital converter. As you know, such analog-to-digital converters have limited speed due to the limited counting speed of binary and reverse counters. In addition, such analog-to-digital converters have a large dynamic error of the converter, especially manifested in the prototype at the beginning of each stage, for example, when entering the tracking mode and when it is lost during rapid random changes in the input voltage within the implementation of the input signal.

 The aim of the invention is to increase performance while increasing dynamic accuracy.

 The goal is achieved by the fact that a parallel analog-to-digital converter and an analog storage device, the input of which is the input of the entire device, and the output is connected to the inputs of the main and analog inputs, are introduced into the device containing the clock generator, the main analog-to-digital converter, the control unit and the digital-to-analog converter parallel analog-to-digital converters. The first input of the control unit is connected to the control input of the analog-memory device, the second output is connected to the start input of the parallel analog-to-digital converter. The clock frequency is connected to the first control input of the control device and the clock input of the first analog-to-digital converter, the second control input of the control unit is connected to the input signal "End of conversion" (KP) of the main analog-to-digital converter, the output code of the parallel analog-to-digital converter is supplied to the corresponding digital inputs of a digital-to-analog converter, the output voltage of which is supplied to the input of the reference voltage connected to the reference input of the parallel tax-to-digital converter by the value of the weight of its least significant digit. The output of the parallel analog-to-digital conversion code is proportional to the scale, and the output code of the main analog-to-digital converter is an information code.

 A comparative analysis of the proposed technical solution with the prototype shows that the inventive device is characterized by the presence of an analog storage device, an analog-to-digital converter with parallel actions and their connections between themselves and the rest of the circuit elements.

 Thus, the claimed device meets the criteria of the invention of "Novelty." A comparison of the proposed solutions with other technical solutions shows that the analog storage devices and parallel analog-to-digital converters are known.

 It is also known to use parallel analog-to-digital converters of the conveyor type in which they form a rough digital equivalent (high order) of the output code of the device. In the proposed device, a parallel analog-to-digital converter serves only to accelerate the formation of a code proportional to the input convertible voltage, designed together with a digital-to-analog converter to form a reference voltage for the main analog-to-digital conversion. It is also known to use an analog storage device at the input of an analog-to-digital converter to store the current value of the input converted voltage for the duration of the conversion. In the proposed device, an analog storage device is necessary, in addition to the functions indicated above, also for delaying the supply of the converted voltage to the input of the main analog-to-digital converter after the reference voltage is generated, which is proportional to the current value of the input voltage.

 Such a delay does not significantly affect the total conversion time, since in the “Sampling” mode it can be made very small and reduced to the aperture time of an analog storage device, which for high-speed analog storage devices is 100-200 ns or less.

 In addition, the time to establish the reference voltage generated by the high-speed digital-to-analog converter is also small and can be 30-50 ns, since the reference voltage of the main analog-to-digital converter changes after the conversion is completed, i.e., after the final switching of all keys included in its composition digital to analog converter. All this allows us to conclude that the technical solution meets the criterion of "Significant differences".

 In FIG. 1 is a structural diagram of the proposed device for converting voltage to code; in FIG. 2 shows the timing diagrams of its operation, at the points indicated in FIG. 1.

 The device comprises an analog storage device (AZU) 1, a control unit (BU) 2, an analog-to-digital converter of parallel operation (ADC) 3, a main analog-to-digital converter (ADC) 4, mainly bitwise coding, and a digital-to-analog converter (DAC) 5 and 6 clock pulse generator. The input voltage is connected to the input of the analog storage device 1, introduced to store the current value of the input converted voltage for the time of conversion by the main converter 4. The output of the analog storage device 1 is connected to the analog inputs of the parallel ADC 3 and the main ADC 4. To the first control input of the control unit 2 and the clock input of the main analog-to-digital Converter 4 is connected to the clock frequency of the generator 6 clock pulses. The second control input of the control unit 2 is connected to the output signal "End of conversion" of the parallel analog-to-digital converter 4. The first output of the control unit 2 is connected to the control input of the analog storage device 1, the second to the start input of the analog-to-digital converter 4, and the third output of the block 2 control is connected to the start input of the parallel analog-to-digital Converter 3, entered to obtain a code proportional to the value of the input converted voltage. The digital outputs of the parallel analog-to-digital converter 3 are connected to the corresponding digital inputs of the digital-to-analog converter 5, the output of which is connected to the reference voltage input of the analog-to-digital converter 4. The value of the reference voltage connected to the reference input of the digital-to-analog converter 5 is greater than the value of the reference voltage connected to the reference the input of the parallel analog-to-digital Converter 3, the value of the weight of its least significant digit. The digital outputs of the parallel analog-to-digital converter 3 are the outputs of a code proportional to the scale of the input voltage, and the digital outputs of the main analog-to-digital converter 4 are the outputs of the information code.

The device operates as follows. From the corresponding output of the control unit 2 to the start input of the parallel analog-to-digital Converter 3 receives a trigger pulse (Fig. 2A). Simultaneously with the launch of the ADC 3, the analog storage device 1 by the control unit 2 is transferred to the sampling mode of the input signal. After the conversion time of the parallel ADC 3 t _pr1 (Fig. 2 b), the code on the digital outputs of the latter is reliable and supplied to the digital-to-analog converter 5. In accordance with this code, the reference voltage U _op (Fig. 2 g) is supplied to the DAC 5 output the input U _op ADC 4. The value of the reference voltage supplied to the DAC 5, selected more than the reference voltage supplied to the parallel ADC 3, the weight of the least significant digit of the ADC 3 to avoid overflow in the output code of the main ADC 4. Since The use of this reference voltage occurs during the "Sampling" mode of the RAM 1, a transient process with time t _lane (Fig. 2 g) occurs before the start of the parallel ADC 4 start, then it does not affect its operation. At the end of the "Sampling" mode of the ACU 1 after the time t _in (Fig. 2, c), the ACU 1 is transferred by the control unit 2 to the "Storage" mode (Fig. 2, c), it simultaneously starts and starts the conversion of the ADC 4 (Fig. 2 , e). The conversion occurs with a reference voltage U _op (Fig. 2, g), proportional to the fixed AZU 1 current value of the input voltage U _I device. At the end of the conversion time of the ADC 4 t _CR2 (Fig. 2, d) by the signal "End of conversion" (KP) (Fig. 2, d), the control unit 2 transfers the AZU 1 to the "Sample" mode. At the digital outputs of the parallel ADC 3 there is a code proportional to the scale of the input converted voltage N _m , and at the digital outputs of the main ADC 4 there is an information code N, _and then all the processes described above are repeated again.

 The advantage of the proposed device in comparison with the prototype is to increase the speed of the device, since the code used to form the reference voltage for the main (information) ADC is formed by the ADC of parallel action, which reduces the total conversion time. In addition, the main ADC can be any “fast” ADC, both bitwise coding and parallel operation. Another important advantage of the proposed device is to increase the dynamic accuracy of the device and the combination with a parallel analog-to-digital Converter.

Claims (1)

 VOLTAGE CONVERTER TO A CODE containing a clock generator, a main analog-to-digital converter, the outputs of which are the first output bus, and the reference voltage input connected to the output of the digital-to-analog converter, the reference voltage input of which is the first reference voltage bus, the main analog-to-digital trigger input the converter is connected to the first output of the control unit, characterized in that, in order to increase speed and dynamic accuracy, analogs are introduced into it o-digital converter of parallel type and analog storage device, the input of which is the input bus of the device, the control input is connected to the second output of the control unit, and the output is connected to the analog inputs of the main analog-to-digital converter and analog-to-digital converter of parallel type, the outputs of which are connected to the corresponding inputs of the digital-to-analog converter are the second output bus of the device, the second bus of the reference voltage of which is the input of the reference voltage a parallel-type tax-to-digital converter, the clock input of which and the clock input of the main analog-to-digital converter are connected respectively to the third output of the control unit and the output of the clock pulse generator, the output of which is also connected to the first input of the control unit, the second input of which is connected to the "End of conversion "the main analog-to-digital converter.

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