SU1197075A1 - Analog-to-digital converter - Google Patents

Abstract

Analog-digital converter comprising masshtabirukntsih amplifiers .The inputs which are combined and input yuinoy, and outputs connected respectively to the inputs 1I pervv uzkodiapa- band analog-to-digital converters, which are connected respectively with the output inforiatsionnvsh switch inputs, the outputs of which are code tires mantissa, and W11ravl yod (and their inputs, with outputs, pre-form a unitary code into a single positional code, differing in that, in order to improve accuracy, a generator is introduced into it pulse, frequency divider, delay element, delay block on n-1 counter, two registers, unit position code converter to binary position code, n-1 OR elements, whose inputs are connected respectively to the high-order outputs of the corresponding narrow-range analog-to-digital converters, and Lasers with corresponding first inputs of the first register, the second input of which is connected to the output of the delay element, the input of which is combined with the input of the frequency divider and the second inputs of the narrow-band aia log-converter converters and connected to the generator output from clock pulses, while the inverse outputs of the first S register are connected to the first inputs of the second register, the second inputs of which are connected to the direct outputs of the first register respectively, and the second inputs of the counter are connected and connected to the output of the frequency divider, with the codes of the second register being connected respectively to the inputs of the converter of the unitary code into a unit position code, the subtractors of which are connected respectively - ve but to the inputs of the converter ediel-border positional code in binary position code, the outputs of which are code tires order.

Description

The invention relates to a measurement technique and is intended to convert an input voltage, changing in a wide dynamic range, into a code.

The purpose of the invention is to improve the accuracy of conversion of signals varying over a wide dynamic range from a level commensurate with the drift of scaling amplifiers,

The drawing shows a schematic diagram of an analog-to-digital converter.

Analog-to-digital converter (ADC) contains input bus 1, mainstabilizing amplifiers 2n, oscillator 3 sync pulses, narrow-band ADC 4 (- 4h, switch 5, elements OR 6, - 62, element 7 delays on odnzibratoy payj frequency divider 8, first register 9, block 10 delay on the counters 11; | - 11, the second register 12, the converter 13 unitary code into a single positional, the converter 14 unit, the position code into binary positional.

Works analog-to-digital Converter as follows.

The input signal, which varies in a wide dynamic range, is fed to a set of amplifiers Z is amplified by S K, K and 1 times, moreover, K 2, where a is an integer. These scaled signals are converted into a digital code using narrow-band ADCs 4–4 according to the synchronization pulse from the clock generator 3. Simultaneous launching of the ADCP is required to reduce the dynamic error caused by the asynchronous sampling of the values of the converted ADC signals. The presence of 1 in any higher category de UARP, starting from the 2nd, indicates an overload of a more sensitive ADCP. The signals from the outputs of the higher bits of the UARP 4, pass through the CM 6 | - 6 elements are set to 1 the corresponding bit of the first register 9 according to the sync pulse delayed by the delay element 7. If 1 is set to one or more bits of the first due to an overload of the sensitive ATsP register 9, then the signal from the direct output of these registers is reset to the corresponding counter g of the delay unit 10, and the inverse output signal is set to one the corresponding bit of the second register 12, the outputs of which passed the unitary converter 13 ode in a single position, control the operation of the switch 5, ie. e prohibit passage of bit signals on more sensitive UATSP ADC output bus (bits mantissa code vyhodngo). When the input signal is reduced to a level at which it enters the working area of a more sensitive UAC (this UAC has been overloaded and cannot function normally for some time Td until its transient process ends in its scaling amplifier, and the duration of the transient process T can be defined as

T.ten (Ue ,,,, jh)

where c is the time constant of the dividing chain of the amplifier — the maximum level of the UACP signal being converted; h is the value of the ADCP quantum, will return to the initial zero state of the correspondences of the bit of the first register 9 and the pulses from the frequency divider 8 will begin to fill the corresponding, the counter 11, 11 of the delay unit Yu and the counter will count down the time necessary for recovery to normal The power amplifier, which was 11th up to this point, was overloaded. If the input signal does not cause a new overload of this amplifier, then after time T, the pulse at the overflow output of the corresponding counter of the delay unit 10 will be set, which will set the corresponding second register 12 to O and only after this signal will the signals from the outputs of the more sensitive ATAC go through the switch 5 to the output of the ADC. If, on the time interval TQ, when the corresponding counter .11, -11 is filled, the input signal overloads the amplifier again, the signal from the corresponding bit of the first register 9 will reset counter 11 and the ADC will go to the state that has already been considered. Such an implementation of the algorithm for selecting the corresponding UACP allowed - ::. It is possible to exclude errors, caused by overloading of amplifiers. The signals from the output of the converter unitary code 13 to unit 1197075 positional after converting them to the binary position code of the converter 14 are the highest bits of the ADC (bits of the order).

Claims (1)

ANALOG-DIGITAL CONVERTER containing η scaling amplifiers, the inputs of which are combined and are the input bus, and the outputs are connected respectively to the first inputs of the narrow-range analog-to-digital converters, the outputs of which are connected respectively to the information inputs of the switch, the outputs of which are the mantissa code buses, and the control inputs - with the outputs of the unitary code converter into a single positional code, with the fact that ^ in order to increase accuracy, a synchronization generator is introduced into it pulse, a frequency divider, a delay element, the delay unit on the n-1 counter, two registers, the inverter unit povhodom frequency divider and a second input narrow band analog-to-digital converters and connected to the output of a generator of n inhroimpulsov, wherein the inverted outputs of the first. g of the register are connected to the first inputs of the second register, the second inputs of which through the corresponding counters are connected respectively to the direct outputs of the first register, and the second inputs of the counter are combined and connected to the output of the frequency divider, and the outputs of the second register are connected respectively to the inputs of the unitary code converter into a unit position code the outputs of which are connected respectively to the inputs of the converter of a single positional code into a binary positional code, the outputs of which are code buses order. >