RU1802413C - Follow-up analog-to-digital converter - Google Patents

Abstract

The invention relates to measuring technique and can be used to improve the accuracy of the following type of analog-to-digital converters. An analog-to-digital converter comprises a comparator, a digital-to-analog converter, a trigger, a pulse generator, a first AND element and a first reversible counter. To increase the resolution of the conversion, a control unit, a second AND element, and a second reversible counter are introduced into it. The resolution is increased due to the fact that, while maintaining the selected conversion range, the conversion result is obtained by a pronounced code with a low-order weight that is two times less than before using the proposed technical solution. 1 s.p. f-ly, 4 ill.

Description

The invention relates to measuring technique, which can be used to increase the accuracy of the following type of analog-to-digital converters.

The aim of the invention is to increase the resolution of the conversion.

Figure 1 shows an example of the proposed implementation of the ADC. Fig. 2 is a timing chart of the operation of the control unit. Figs. 3 and 4 show the operation algorithms of the proposed converter for a software implementation by using computer resources.

The analog-to-digital converter (Fig. 1) contains a comparator 1, a digital-to-analog converter 2, a trigger 3. a second reverse counter 4 pulses and a control unit 5, a pulse generator b, the first 7 and second 8 elements And, the first reverse counter 9. Block 5, the control comprises first 10, second 11 and third 12 AND element, OR element 13, first 14, second 15, third 16 and fourth 17 delay elements.

In the initial state, the converter is held by a forced reset applied to the zero inputs of trigger 3 and counters 4 and 9 of pulses. The codes on the information outputs of counters 4 and 9 of pulses are equal to zero. Equal to zero and the analog signal at the output of the converter 2.

The analog-to-digital converter is put into operation by removing the Reset signal. In this case, the pulse counter 9 will be in a state capable of responding to pulse signals supplied through the elements 7 and 8 from the pulse generator 6.

An analog-to-digital converter operates as follows.

Since at the moment of start-up, the convertible signal acting on the first input of comparator 1 is superior to the compensation signal supplied to its second input from the output of digital-to-analog converter 2, the logical unit will be the signal at the direct output of comparator 1. The signal at the inverted output of comparator 1 will be equal to zero. Therefore, after starting the converter, pulses from the pulse generator b will be fed to the summing input of the pulse counter 9, the contents of which will increase.

This process will continue until the compensating voltage acting on the second input of the comparator 1 exceeds the convertible

signal acting on its second input. After that, the signal at the direct output of comparator 1 will take a value of zero, and the signal at its output will be unity.

On the leading edge of the signal of the inverted output of the comparator 1, received at the input of the installation of the trigger unit 3, the latter will generate a signal, expressed by a logical unit, about the output of the converter to the addition mode.

This signal will be received at the input of the control unit 5 as the signal End of conversion (KP-1) and will prepare the And 10 element for passing pulses from the 6 pulse generator that are fed to the second input of And 10 through the delay element 15.

The pulse from the output of the 6 pulse generator, which caused the switching of control signals at the output of the comparator 1, through the delay element 15 and the And 10 and OR 13 elements gets to the reset input of the zero pulse counter 4, which ensures (confirms) the reset of the latter.

5 Being delayed by the delay element 14, this pulse will be fed to the synchronization input of the counter 4 pulses, whereby information acting on its counter will be entered into the counter 4 pulses

0 inputs of the initial installation.

In this case, zero will be entered in the low order of the counter 4 pulses, and in its higher order, starting from the second, the code resulting from the conversion,

5 which is equivalent to performing a left shift operation by one.

Thus, a code twice as large as the code valid at the input of the counter 4 pulses will be entered into the 4 pulse counter. Next, the pulse from the output of the delay element 14 will go to the input of the delay element 17 and, being the last delayed while the code is being entered into the pulse counter 4, it will go to the subtracting input of the counter

5 4 pulses, the contents of which will decrease by one.

Delayed by the delay element 17 for the response time of the counter 4 pulses, the considered pulse will arrive at

0 clock output of the proposed analog-to-digital converter, on the information output of which a code is valid. generated in the counter 4, and being the final result of the conversion, closer to the converted value than the code received in the counter 9 pulses.

The second, after the considered one, the pulse from the output of the b pulse generator will go to the input of the And 8 element, at the second

the input of which continues to operate the control signal from the inverse output of the comparator 1.

As a result, the contents of the counter 9 pulses will be reduced by one. Accordingly, the compensation voltage acting on the second signal input of the comparator 1 will be changed,

Further, depending on the ratio of the signals at the inputs of the comparator 1, the last signal will be added or the signal reduced and the procedure described above will be performed.

In this case, the code entered in the counter 4 pulses will decrease or increase by one depending on which of the two control outputs of the comparator 1 a logical unit has been generated. Logical unit at the inverted output corresponds to a decrease by unit of the contents of the counter 4 pulses. The logical unit at the direct output to add corresponds to an increase in the unit of the contents of the counter 4 pulses.

It should be noted that the total delay provided by the delay elements 14, 15, 16, 17 must not exceed the period of the pulse sequence generated by the pulse generator 6.

The delay provided by the elements 14, 16, 17 of the delay will be small, because necessary for performing transients with a digital counter element. The delay of element 15 is determined by the total delay of blocks 5.1, 1.

Using the proposed device in the national economy will allow a simpler, and therefore cheaper way, to increase the instrumental reliability of the device when converting analog values to digital codes, i.e. to increase the resolution due to the fact that, while maintaining the selected conversion range, the conversion result is obtained by a pronounced code with a low-order weight that is two times less than before using the proposed technical solution. For example, using an ADC with a 10-bit DAC, it will be possible to get an 11-bit code at the ADC output.

FORMULA AND SECTION

Claims (2)

1. The next analog-to-digital converter containing a comparator, the first input of which is the input bus, and the second input is connected to the output of the digital-tax converter, the information inputs of which are connected to the corresponding information outputs of the first reversible pulse counter, the addition input of which is connected to the output of the first element And, the first input of which is connected to the output of the clock generator, the inverse output of the comparator is connected to the installation input of the trigger unit, characterized in that then, in order to increase the resolution of the conversion, a control unit, a second I / I element and a second reversible pulse counter are introduced into it, the information outputs of which are the corresponding output information buses, and the inputs of the initial setting of high-order bits are connected to the corresponding information outputs of the first reverse pulse counter, the subtraction input of which is connected to the output of the second element And, the first input of which is combined with the first input of the control unit and connected to the output of the gene clock pulse generator, and the second input is combined with the second input of the control unit and connected to the inverted output of the comparator, the trigger output is connected to the third input of the control unit, the fourth input of which is combined with the second input of the first AND element and connected to the direct output of the comparator, the input of the initial installation the low-order bit of the second reversible pulse counter is a zero potential bus, and the synchronization input of the initial installation is connected to the first output of the control unit, the second output of which is connected with the installation input in О of the second reversible pulse counter, the addition and subtraction inputs of which are connected respectively to the third and fourth outputs of the control unit, the fifth output of which is the signal line of the conversion end, and the fifth input is combined with the inputs of the installation in О of the trigger and the first reversible pulse counter and is the Reset bus. 2. Converter pop. 1, and the fact that the control unit contains four delay elements, three AND elements and an OR element, the output of which is the second output of the control unit, the fifth input of which is the first input of the OR element the second input of which is combined with the input of the first delay element and is connected to the output of the first element And, the first input of which is the third input of the control unit, and the second input is connected to the output of the second delay element, the input of which is the first input of the control unit, the third and fourth exits which are the outputs of the second and third elements, respectively, and the first inputs of which are respective delays, the input of which is connected to the fourth and second inputs of the first delay element, which is the control unit, and the second inputs are combined by the first output of the control unit, yen with the input of the third element, the delayed output of which is the output and connected to the output of the fourth element 5 of the third delay element. CSpoc .Kp1 (8th element.Z) Exit element. fifteen U1, count. y (cspoc., tl-i | MEfi.15 --- W- Bx. Ч cf. Yu {Zatsb) B AND G „And I -Out. ale. sixteen - &. + SC-U -SUM. angry. P H ((8b, H. elem. 17) j 11.11T Cn FIG. 3 Keep track of the youngster preiorazodate / L Delay t-j Delay fy