SU1547067A1 - D-a converter - Google Patents

Abstract

The invention relates to automation and computing and is intended to build digital information to analogue converters. The purpose of the invention is to increase accuracy. The digital-analog conversion device contains a digital adder 1, the first 2 and second 3 switches, the first 4 and second 5 digital-analog converters, and an analog adder 6. A positive effect was achieved by introducing a digital adder and performing the first switch in three positions, which made it possible to eliminate the nonlinearity of the conversion characteristic the middle of the scale. 1 il.

Description

one;

(21) 433Й73 / 24-24

(22) 11/20/87

(46) 02.28.90. Bul VF 8

(71) Penza Polytechnic Institute

(72) A.A.Lomovtsev, V.P.Safronov, B.P.Sibrinin and S.V.Trubitskov (53) 621.385 (088.8)

(56) Fedorkov B.G. and others. Microelectronic digital-analog and analog-to-digital converters. M .: Radio and Communications, 1984.

U.S. Patent No. 4,473,818, cl. H 03 M 1/66, published in 1984.

(5) DEVICE OF DIGITAL ANALOGUE TRANSFORMATION

No scratch code

(57) The invention relates to automation and computer technology and is intended to construct digital information transducers in analog. The purpose of the invention is to improve accuracy. The digital-analog conversion device contains a digital adder 1, the first 2 and second 3 switches, the first 4 and second 5 digital-analog converters, and an analog adder 6. A positive effect was achieved by introducing a digital adder and performing the first switch in three positions, which made it possible to eliminate the nonlinearity of the conversion characteristic the middle of the scale 1 Il.

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Minor Dip

code

Senior bit

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The invention relates to automation and computing and is intended to build digital information to analogue converters.

The purpose of the invention is to improve accuracy.

The drawing shows the functional diagram of the digital-analog conversion device.

The digital-to-analog conversion device contains a digital adder l, a first 2 and a second 3 switch, a first 4 and a second 5 digital-to-analog converters (DAC), and an analog adder 6.

The device works as follows.

An n + 1 bit shoe goes to the input bus of the transform code. Senior n + 1th bit is used as a control signal. With a Zero value of the most significant bit of the Convertible code, the first switch 2 connects the inputs of the first n-split DAC 4 to the input bus of a zero-feoro code, and the second switch 3 connects to the inputs of the second n-bit bottom of the DAC 5 n younger bits of the transformed | code. As a result, the first output of the analog adder 6 from the DAC output k is a zero level signal, and the second input is a signal from the DAC 5 output proportional to the value of the low-resolution bits of the code to be converted.

 At the moment of changing the value of the converted code from 011 ... 1 to 100 ... O, the signal level from O to I1 changes at the control input of the second switch 3, as a result of which a single code is connected to the inputs of the second DAC 5, duplicating the previous value of the lower bits of the code to be converted, which eliminates the occurrence of a signal surge at the output of the DAC 5. At the same time, at the first control input of the first switch 2, the signal becomes 1 (at the second control input of switch 2, the signal is O) and switch 2 connects the DAC inputs k to the outputs of the digital adder 1. At the first inputs of the digital adder 1, the lower bits of the converted code, and the low bit of the second inputs of adder 1 is given the high bit of the code to be converted. Ostal

five

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five

five

0

0

five

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five

The second bits of the second inputs of the adder 1 are connected to the zero potential bus. At the output of the digital adder 1 (and at the inputs of the first DAC L) a code 00 ... 01 is formed, as a result, the signal at the output of the analog adder 6 is increased by an amount proportional to the unit of the least significant bit, and the total signal at the output of the device becomes proportional to the weight older bit of the code to be converted.

With further increase of the converted code at the output of the DAC 5, the signal does not change, and at the output of the DAC k, the signal grows in proportion to the value of the lower bits of the converted code. When the converted code reaches the value ... 110 at the output of the digital adder 1 and the inputs of the digital-to-analog converter, the code 11 ... 111 is formed, while the maximum value of the signal takes place at the output of the digital-analog converter And the total signal at the device output is equal to the sum of the maximum output values DAC signals k and 5. When the input code is 11 ... 111, the overflow output of digital adder 1 generates level 1, as a result of which the inputs of the DAC k through switch 2 are connected to the unit code bus and the signal value at the output of the DAC 4 does not change .

Thus, a digital-analog conversion device converts an nH-bit code into an analog signal with a maximum value proportional to a code value of -2, while eliminating the non-linearity of the conversion characteristic in the middle of the conversion scale inherent in the prototype device, and there is no overshoot , output signal at the main code transition of the converted signal.

The first switch 2 may be implemented, for example, in an n-bit register. When applying to the inverse zero input (input R) of the level O register, a zero code is formed at its outputs, and at level 1, a unit code is formed at the output of the installation (input S). A digital code from the information inputs of the register is transmitted to its outputs when a pulse signal arrives at the clock input, while the inputs R and S must be present

signals 1 and O, respectively. The second switch 3 can be implemented in the same way, in this case the input R is not used.

Claims (1)

Invention Formula 15 A digital-to-analog converter device containing the first and second switches, the first and second digital-analog converters, and an analog adder, the output of which is an output bus, and the first and second inputs are connected to the outputs of the first and second digital-to-analog converters, the inputs of the last of which are connected with the corresponding outputs of the second switch, the first information inputs of which are the input bus of the lower bits of the code being converted, and the second information inputs are the input bus of a single code, the outputs of the first switch are connected to the corresponding inputs of the first digital-to-analog converter, th 5470676 For the first time, the information inputs are the input bus of the zero code, and the first control input is combined with the control input of the second switchboard. For the purpose of improving accuracy, a digital adder has been entered in it, the first inputs of which are combined with the corresponding first information inputs of the second switch, the second inputs, besides the lower potential input, are connected to the zero potential bus, and Yes, the second 15 OUTPUT inputs are combined with the control input of the second switch and is the highest bit of the input bus of the code to be converted. The information outputs of the digital adder are connected to the corresponding second information inputs of the first switch, and the overflow output is connected to the second control input of the first switch, the third information 25 inputs of which are connected to the corresponding inputs of the input bus of a single code.