SU819953A1 - Method of parallel-series analogue-digital conversion - Google Patents

Description

The invention relates to a pulse technique and can be used to create analog-to-digital converters of a parallel-series type with improved speed.

There is a method of parallel-serial analog-digital conversion, which consists in the fact that in the first cycle the input analog signal is converted by comparison with the main one. The reference / 1 signals are converted into binary code signals, which are memorized, and in the second and subsequent cycles, the signals of this code are converted into analog feedback signals, which are then scaled and added, after which the total analog feedback signal is subtracted from the input analog signal , this difference signal is amplified and transformed, as in the first cycle, into binary code signals, which also memorize, l.

However, in this method, the transformation time at each clock cycle is determined.

maximum possible; the range of variation of the amplified signal of the difference between the converted signal and the feedback signal, which leads to an increase in the average conversion time.

The aim of the invention is to increase the speed of the analog digital conversion.

This is achieved in that in the method of parallel-serial conversion, which consists in converting an input signal in the first cycle by comparing with the main reference signals into signals of a binary code, which are stored, and in the second and subsequent cycles of this code are converted into analog signals feedback, which then scale the sum, after which the total analog feedback signal is subtracted from the input analog signal, this time the BONE signal is amplified and converted as in the first m tick, in binary signals

codes that also store, at the beginning of the second and after cycles, change the weighting factors of the analog feedback signals, while the analog feedback signals are summed with the second auxiliary reference signal and the total reference signals, the total the analog feedback signal is formed by summing the feedback signals with the first auxiliary reference signal, and at the beginning of the third and subsequent clock cycles change lighting reference signals.

In this method of parallel-serial analog-digital conversion by introducing operations to change the weighting coefficients of scaling analog feedback signals and adding an auxiliary signal that is summed with the input signal, while the scales of the reference signals are simultaneously shifted, the level of the output signal after amplification of the difference signal remains unchanged , if the value of the latter is proportional to half the quantum of the scale of a given conversion cycle, the id of the remaining values of the difference the signal level of the amplified signal can be varied within only half of the possible variation range. Thus, the change in the amplified signal during the transition to the next conversion wave is two times less than the analogous change in the amplified signal in this known method.

When this cnoct a is implemented, a technical repair leads to a proportional decrease in the execution time in each step of the analog-to-digital conversion, i.e., to increase its speed, the latter being achieved without changing the gain of the analog signals and without improving the accuracy of the comparison operation of the analog signals. signals with reference.

FIG. 1 is a block diagram of a three-stroke analog-to-digital converter; in fig. 2 - time diagram of his work.

The block diagram contains an analog switch 1, an amplifier 2 with controlled gain, a read converter 3, a block of reference signals 4, a section register counter 5, first and second digital-to-analog converters (DAC) 6 and 7, a control block 8,

block 9 of the formation of auxiliary reference signals, the first and second scaling units 1O and 11, the first and second analog adders 12 and 13, the bus analog input 14, the interface inputs-outputs 15 of the control unit 8 ..

FIG. 2 The following symbols are taken into account: 16 — the impulse of the initial state, generated at one of the outputs of the control unit, according to which the conversion starts; 17 and 18 - signals at the outputs of the first and second DAC 6 and 7; 18 - signal at the output of amplifier 2; 20 and 21 are the initial and final levels of the output signal of amplifier 2 at the first conversion cycle; 22 and 23 — specific and maximally possible time intervals, during which the signal changes at the output of amplifier 2; 24 - output pulses of block 8, which are used to read the code from the output of converter 3 into register-counter 5; 25 and 26 — Maximum possible time intervals during which variations in the output signal of the amplifier may occur in the second and third conversion cycles; 27 shows the pulses at the interface input 15 of block 8, which is allowed. transfer of the result code to convert.

The analog-to-digital conversion in this converter is performed as follows. First, the control unit 8 generates a pulse of the initial state 16, by which the counter 6 and the auxiliary reference signal generation unit 9 are extinguished, and in amplifier 2 the smallest gain factor K 1 is set. Since the output signals of the DAC 6 and 7 are zero and absent the output signal of block 9, the input, the signal of amplifier 2, coming from the output of the analog subtractor 1, is equal to the input analog signal supplied to the first input of the subtractor 1 via the input analog bus 14. As a result, the output of the amplifier 2 is output This signal starts to change from the previous value (level 20) and is set after a time interval of 22 at level 21, which corresponds to an input analog signal.

Claims (2)

The output of amplifier 2 is fed to the input of read converter 3, in which it is converted into parallel-binary signals. After the time interval 23 has elapsed since the signal 16 appeared, signal 24 received from block 8 reads this binary code and writes it to the high bits of the counter register 5. If the value of the coa read from the outputs of the converter 3 differs from zero, the output 17 of the first D / A converter 6 begins to change, which after some time is set at a level corresponding to the accuracy of the conversion cycle input to the analog signal. Simultaneously with the reading of the K-bit code in the register-counter 5, the block 8 begins to prepare the second conversion cycle. In this case, in amplifier 2, the gain is set to 2 times greater than in the first cycle, the inputs are opened for reading the code from the outputs of converter 3 to the middle bits of register counter 5, the scaling factor in block 1O is set to (1 - 1/2), and in block 9 the following values of auxiliary signals are set: the first (for shifting the output signal, hiccup 2) and -AlC-ia) and the second (for shifting the scale of block 4 and, - ЛА-2 - where D. А g Aq- / 2 is the quantum of the input analog signal, Аa is the range of the input analog signal signal The signal at the output of converter 6 begins to change, and after it begins to change and the signal at amplifier 2 output. With the above values of the scaling factor and the first additional reference signal, the maximum possible change at the output of amplifier 2 is halved compared with a similar signal in a converter made on the basis of a known method and containing an analog subtractor connected by an output through an amplifier with a controlled gain factor and a transducer azovatel read from the register inputs, the outputs of which through a digital to analog pre-forming a first input connected to the analog subtractor, a second input coupled to the analog input bus, wherein the control unit outputs are connected with the control inputs of said amplifier and the register. Indeed, suppose that the input signal has the value A A (), where H, obtained in the first conversion cycle. The output signal of the block 10 ASC., | taking into account the scaling will be equal to D A M (1 -). Then, for a fixed value of Y y: (1, P) of the signal at the output of amplifier 2 at the transition from the first to the second conversion cycle and with the presence of the feedback signal AQJ. - Asch, - C, you can write the following expression: A, (I, ri) - (A,) (N ,. N / g DAY C -tszM AACA-IgM -2 - l. A (N 1-1 / 2 Thus, at the indicated values of the input analog signal and the general feedback signal, no change occurs at the output of amplifier 2. In the case when the input analog signal differs from the value of Lt (N / t + 1/2), i.e. it is in the range from .A to (N +1/2) YES or from () YES to (N +1) YES, then the change in the output signal during the transition from the first to the second cycle will not exceed A y / 2 . When the input signal is N lА or. + L) Л А there will be the greatest change output amplifier 2. This is a change, a failure for AYH (will be equal to (l.lDwakt-Ay (1, P) Aaks- (K 1-LdA YES; 2 - 1H-1 /, that is, almost two times less than This transducer is based on a known method. Decreasing the output signal range leads to an equivalent reduction in the maximum possible signal setup time at the amplifier output to the conversion clock, hence the transducer speed improves. to the second measure its maximum possible change to A / 2, the code is read from the outputs of the converter 3 to the middle K-bits of the register. It should be noted that this time interval is slightly longer than the same interval 23 of the first clock cycle, since changing the gain of the amplifier 2 changes 2 times The rate of change of the signal at the amplifier output is also explained by the fact that real amplifiers are equivalent to the PC link, in which, simultaneously with an increase in the gain factor, the value of the resistance P increases, which um to increase the time constant of such a link. In preparing the third conversion step, block 8 sets the gain of amplifier 2 to 2 and also generates signals that control the change of the scaling factor in blocks 1O and 11 and change the output signals of block 9. To store the change in output signal of amplifier 2 not exceeding A (/ 2, also when converting to the third cycle, the value of the first supreme reference signal is set equal to 1/2 (1 - 1/2) LA, the scaling factors in the Yun units 11 are set equal to (1 - 1/2) and (1 - 1/2), in the meaning of the second auxiliary reference signal, is set equal to Л А (г +1) if the input signal matters), where N {.- code, received in the second and the second transformations, the output signal of the amplifier 2 will not change when going to the third cycle. It is similar to what happens when going to the second time step of the input signal equal to / SA (). After a time interval of 26, equal to the maximum time for establishing the signal at the output of amplifier 2, which is determined by the new value of the time constant, which has changed (increased) with a change in the gain during the transition from the second to the third conversion clock, the code is written from the outputs of the converter 3 in the lower order, the bits of the register 5. At this point, the process of the three-cycle analog-41 conversion is finished, and the result code of the conversion from the outputs of register 5 can be transferred to the microprocessor according to The following is the output signal of the conversion result transferred from block 8 one by one to the outputs 15. In the general case, for the AND-contact reversal of the proposed method, the following expression for the feedback feedback AQ. Al-i / a is valid. - 1 |, (... and. Here, the coefficients at D determine the value of the scaling coefficients of the scaling blocks, and the last term of the expression is the value of the offset signal at each conversion cycle. The offset signal of reference levels of comparison J, generated by block 13, in the considered converter is determined by the following expression: CMj × | i (jH) (. | 2). In these terms, LA is the quantum at the first conversion cycle; - the value of the conversion codes on the switch of the i-th cycle; 1-1, 2, (j - 1); K is the number of concurrently received code bits in each conversion cycle. Thus, in the h-cycle parallel-serial converter, made on the basis of the considered method, in which the formation of signals and, | In accordance with the above formulas, the maximum possible change in the output signal of amplifier 2 at each conversion step is halved compared with the above-mentioned converter based on the known conversion method. This is equivalent to almost the same reduction in the execution time of each conversion cycle, i.e., a nearly twofold increase in conversion speed. In doing so, the implementation of the newly introduced non-Tpe6yeTi operations using more high-speed elements and nodes than those on which the specified known converter is performed. The invention of the method of parallel-to-serial analog-to-digital conversion is that in the first clock re the analog input signal is converted by comparison with the main reference signals into binary code signals that are stored, and in the second and subsequent clock cycles the signals of this code are converted into analog signals feedback, which then scales and sums; after that, the total analog feedback signal is subtracted from the input analog signal, this difference signal is amplified and converted, as in the first clock cycle, into binary code signals, which are also memorized, characterized in that, in order to increase the speed of the analog signal the digital conversion, at the beginning of the second and subsequent clock cycles, change the weighting factors to scale310. analog signal feedback signals, simultaneously analog signals. the feedbacks are summed with the second auxiliary reference signal and changed by the magnitude of this total signal all the main reference signals, the common analog feedback signal, are formed by summing the feedback signals with the first auxiliary reference signal, moreover, at the beginning of the third and subsequent clock cycles change auxiliary reference signals. Sources of information taken into account in the examination 1. GM Petrov. Transformation of information in analog-digital computing devices and systems, M .; Mechanical Engineering, 1973, p. 247 (prototype). 6 Yj 17 Jl / 3 n 4 21 Fog.