SU1257848A1 - Digital-to-analog converting device - Google Patents

Abstract

The invention relates to the field of computing and digital measurement technology and can be used to convert digital values to analog ones. The invention makes it possible to increase the accuracy of digital-analog conversion by improving the linearity of the conversion characteristic. An increase in linearity of the conversion characteristic is provided by the input of the arithmetic logic unit and the second switch, which allow to take into account the deviation of the actual weights of the digital-to-analog converter bits from the required, corresponding to the weights of the redundant measuring code, in the process of converting the input code into an analog signal. 1 hp f-ly, 4 silt, 1 tab. § (L yul 00 4 ;; CX)

Description

The invention relates to computational and digital measuring technology and can be used to convert 1-dimensional values to analog ones.

The purpose of the invention is to improve the accuracy by improving the linearity of the conversion characteristic.

FIG. 1 shows a functional diagram of a digital-analog conversion device; in fig. 2 - functional scheme of the control unit; in fig. 3 and 4 is a graph-diagram of the algorithm of the device.

The digital-to-analog conversion device (Fig. 1) contains arithmetic logic unit 1 (ALU), bus 2 of the code to be converted, the first and second digital switches 3 and 4 (CC), the first and second registers 5 and 6 (RG), and a permanent memory. device 7 (ROM), random access memory 8 (RAM), digital-to-analog converter 9 (TsA11), block 10 of the analog storage device (BASE), block 11 of comparison (BS), sequential approximation register (BS), shift register 13 (CWG) control unit 14. (CU), the device output bus 15, the first and second control buses 16 and 17, which are connected to the first and second inputs of the control unit 14, the Start bus, which is connected to the third input of the control unit 14. The latter also has quarter and sixth entrances 18 and 19 and fourteen exits 20-33 "

The control unit 14 comprises first and second registers 34 and 35, a clock pulse generator 36 and a persistent storage device 37.

Digital to analogue Converter 9 of the proposed device must be made on the basis of redundant measuring codes (CC).

The presence in the bits of the converter, built on the basis of the KII, deviations of the weights of the bits from the required values in the limited limits do not lead to discontinuities of the output characteristic, although the latter will be abrupt. For example, when constructing a digital computer graph on the basis of the golden ratio code, or the phononacci, there will be no discontinuities of the output characteristic if the bit weights are

to produce with an accuracy not worse than 23.6%.

The proposed device operates in two modes: verification and direct digital-to-analogue conversion with correction.

In the verification mode, codes of real values of weights of bits of the DAC 9 are determined, and the bits are divided by

the group of senior (top) and per group of the most advanced (non-verifiable) bits. This approach is valid when forming the weights of bits with the same relative error. In STONI

In the case of absolute deviations 4Qj from the required values for large bits will be large, and for younger ones - small. Therefore, the codes of the real values of the weights of the lower-order bits of Kp,

obtained after manufacture of the device, are recorded in ROM 7 and used in operation.

The determination of the Kp codes of the real values of the weights of the bits is made only for the group of I1 higher bits. , The values of m are determined from the condition

1 p. 1 n-mti tr.2

where n is the number of bits of the DAC; Qn-mti deviation from the required ,, - value () of the th digit;

 - values of the first and second Q, P2 lower order bits, respectively.

The codes of real values of weights of high bits are determined by verification and stored in RAM 8. The codes of real values of weights of Cr begin with (n-m + D-ro bits and are carried out sequentially from low-order bits to high. Register 13 the shift ensures the inclusion of a turnable discharge. From the output of the output of the DAC 9, the analog value Qp ,, .. is fed to the BASE 10 and is remembered. Then, the process of partial equalizing of the signal is performed with the prohibition of the inclusion of the turnable discharge Yes. At the same time in DR-1 is generated code r1ealnogo weight value Kr |, which zapisy- vaets in the RAM 8.

In determining the codes of the real values of the weights of the subsequent bits, the real values of

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Codes of codes stored in ROM 7, as well as those determined as a result of verification, and recorded in RAM 8. The verification process ends there.

In the direct conversion mode, all units of the device are involved, with the exception of BASE 10, BS 11, CSG 13, the Input code arriving at the device input buses 2, is written to the second register 6, converted using the ALU 1, ROM 7, RAM 8, PDP 12, WG 5, CC 3, ZDL 9 to the analog output signal Ag ,,. The output signal A 5 is reduced from the output 15 of the device.

The operation of the device in the verification mode is carried out as follows.

Signals from CU 14 reset WG 6, initialize RPP 12, write source code to CWG 13, CC 3 switch to input of DAC 9, CWG 13 output. At output of CLP 9, an analog signal Qp appears, which goes to input BS 11, is stored in BASE 10. The process of balancing Qpr, nm with an input compensating signal DAC 9 A, is performed using the bit-wise encoding method. The prohibition of turning on the turned-off discharge is carried out as a result of analyzing the output signal of the BS 11. Signal 29 BU 14 sets the selection of the ROM cell whose content is fed to the input of ALU 1. The formation of the actual weight value code occurs in ALU 1. 1, through CC 4, it enters the input of WG 6 and is written into it under the action of signal 31 BU 14. By signal BU 14, this code is rewritten into RAM 8. At this, the verification process of the (n-um-1) -th digit ends,

Next, at the commands of the CU 14, WG 6 is zeroed, the CWG 13 is shifted and the next I most significant bit is calibrated. Gaining real weight (g-gm-2) -th spacing484

walks in the same way as above. The verification process ends after determining the codes of the real values of the weights of all high-order bits.

In the direct conversion mode, the device operates as follows.

The input code K is recorded by CC 4 with the help of WG 6 and signals of the CU 14 and compared with the aid of ALU 1 with the real weight code of the highest bit Kp. The comparison analyzes the carry signal Z ALU 1, which is in subtraction mode. Moreover, the transfer signal Z is defined by the following expression:

7 1 b if K, 6: Kp1; i ID if К Кр; . If Z o, then the contents of WP 6 does not change, and in PCH 12, zero is written using the BU 14.

If Zfi 1, the result (a further comparison is made with the remainder C-Cr ") is recorded in WP 4,

and FP12 records one.

The code is then compared with the real weight code, -, the next bit. Further, the conversion of the input code K to the working code Kp occurs in a similar way. The process ends after the n-th comparison of the contents of WP 4 with the real weight code

younger bit

Kt

As a result

in RPP 12, a working code will be generated which, by the signal of BU 14, will be overwritten in WP 5, after which the output 15 of the device will have an analog value A g, j ,, x.

This completes the digital-to-analog conversion of the input value.

The necessary for controlling the operation of the digital-analog conversion device control and conventional signals corresponding to the graph-scheme of the algorithm (Fig. 3 and 4) are given in the table for, m 2.

Address CC 4

Impulse Recording WP 6

Reset WP 6

RAM read / write 8

Address ROM 7 and RAM 8

eight

YO

 h

1g

4j

Selection of ROM 7 and RAM 8 ALU 1 mode

Mode WG 5 Sync Pulse RPP 12

Information entry RPP 12

Initial setting Address CC 3

Shift CGS 13 Sampling base 10.

dd

When Y 1 - input 2 commutes

When Y 1 - record

Y | Y | Ys

101 - 5th bit d 100 - 4th bit d 011 - 3rd bit d 010 - 2nd bit d 001 - 1st bit d

At - sampling ROM 7

When Y 1 - subtraction

When Y. 0 - write

When Y, 1 - switches CSG 13

71257848

With this bit, the control address signal 5 will consist of three signals Y,, Yj, and the actual weight code of the highest (first) bit will be written s at address 101 (Y 1, Y, 0; Yf -1), and the code of the required value of the weight of the lower (fifth) digit will be recorded at address 001 (Y; 1; Y, 0; Y 0).

To the control input of the operational memory of the device, the outputs of which are combined with the outputs of the permanent storage device, the first control input of which is combined with the second control input of the operational memory and connected to the ninth output of the control unit, the tenth outputs

The algorithm consists of (see Fig. 3 and 4): which is connected to the address inputs

vertices 1–2 zeroing of RG 6, initial and permanent memorization of the installation of the CWG 13, sampling of the BASE 10;

vertices 3-15 - encoding Ats with a ban;

vertices 16 - write cr to ram 8j

vershn 17-18 - WG 6 reset, CGS shift 13, BASE 10 sampling;

vertices 19-32 - AS coding with prohibition;

verses 33 - write Kpj to RAM 8;

vertices 34-35 - switching input 2 of the device, giving a write pulse to WG 6;

vertices 36-56 - direct digital-analog conversion.

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the eleventh and twelfth outputs to the first and second control inputs of the second register; the first and second inputs of the control unit are the first and second control slots; the third input is a Start bus, characterized in that To improve accuracy by improving the linearity of the conversion characteristic, an arithmetic logic unit and a second digital switch are introduced, the control input of which is connected to the thirteenth output of the control unit, the first information inputs are busbars of the generated code, the second information inputs are connected to the first outputs

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Claims (2)

1. Digital-Analog Device conversion, containing a digital-30 arithmetic logic unit, a log converter, the output of which outputs are connected to the information device’s output bus and connected to the first input of the comparison unit and the information input of the analog storage device unit and the first information device, output which is connected to the inputs of the arithmetic logic unit, the second input of the comparison unit, the control input - to the first output of the control unit, the second output of which is connected to the first input of the control unit. apominayuschih devices Giustra shift control, which outputs are connected to the input sub fourteenth off to the first data inputs of the first digital switch, the outputs of which are connected to the inputs the inputs of the second register, the outputs of which are connected to the information inputs of the operational memory functions, the second information inputs of which are connected to the combined outputs of the constant and operational the control unit, the fourth input of which is connected to the second output of the arithmetic logic unit, digital-analogue converter, 45 and the fifth input is connected to the output, the second information inputs of the comparison connection, while the outputs are registered to the outputs of the first register, the control input which is connected to the third output of the control unit, the fourth output of which is connected to the control input of the first digital switch, the fifth output to 2. The device according to claim 1, of which is that the highlight control is performed on the first and second registers, the clock pulse generator and the permanent storage the second input of the shift register and the first input of the sequential approximation register, the sixth and seventh output devices, the outputs from first to fourth, to the second and third inputs, the nineteenth, which are connected to the serial approximation register, the eighth output, and the perinformation inputs of the first register Pa, the inputs from the first to the fourth to the second control input of the operational memory of the device, the outputs of which are combined with the outputs of the permanent storage device, the first control input of which is combined not with the second control input of the random access memory and connected to the ninth output of the control unit, the tenth outputs of permanent and operational memory 0 the eleventh and twelfth outputs to the first and second control inputs of the second register; the first and second inputs of the control unit are the first and second control slots; the third input is a Start bus, characterized in that To improve accuracy by improving the linearity of the conversion characteristic, an arithmetic logic unit and a second digital switch are introduced, the control input of which is connected to the thirteenth output of the control unit, the first information inputs are busbars generated code, the second data inputs connected to the outputs of the first five arithmetic logic unit, the outputs are connected to information devices and the first information inputs of arithmetic logic memories, the control input is connected to the fourteenth outputs of the second register, whose outputs are connected to the information inputs of the operational memory arithmetic logic unit, outputs are connected to information devices and first information inputs of arithmetic logic devices, a control input is connected to the fourteenth device, the second information inputs of which are connected to the combined outputs of the fixed and operational The successive approximations are connected to the information inputs of the first register. 2. The device according to claim 1, of which is that the highlight control is performed on the first and second registers, the clock pulse generator and the permanent storage device, the outputs from the first to the fourteenth of which are connected to device, the outputs from the first to the fourteenth of which are connected to information inputs of the first register, inputs one through four, respectively, the first, second, fourth, and fifth inputs of the control unit, inputs from the fifth through the tenth, are connected to the corresponding outputs of the second register, whose inputs are connected respectively to the constant outputs memory device from the fifteenth to the twentieth, the first control input of the second register is the third input of the control unit, the second control input is connected to the direct 1 at the output of the clock pulse generator in the inversion; The output of which is connected to the control input of the first register, the outputs from the first to the third of which are the thirteenth, twelfth and eleventh outputs of the control unit, the fourth outputs are the tenth outputs of the control unit, the outputs from the fifth to the fourteenth are respectively the fifth, eighth, fourteenth, third, seventh sixth, fifth, fourth, second and first outputs of the control unit. Phil Compiled by V.Pelzshikov Editor M.Petrova Tehred L.SerdyukovaKorrector E.Sirokhman Order 6358 Circulation 816 Subscription VESHIPI State Committee of the USSR. for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4