SU822347A1 - Computing voltage-to-code converter - Google Patents

Description

The invention relates to computing technology and can be used in various information measuring systems. . A computational voltage converter into a code is known that contains an encoder switch, whose inputs are connected via an oscillator to the inputs of an analog-to-digital converter, whose outputs are connected to the first group of inputs of the first and second functional converters, and the outputs of the first functional converter are connected to the second group of inputs of the second functional converter, the outputs of which are connected to the inputs of the analog storage device, the outputs of the anoshin storage device A are connected to the output buses of the device; the control inputs of the analog switch, the analog-digital converter, the first and second functional converters are connected to the outputs of the control unit JL. The disadvantages of this device are limited functionality. Also known is a computational voltage converter into a code containing a comparison device, the first input of which is connected to the input signal bus, the second input with the output of a digital-to-analog converter, the inputs of which through a digital switch are connected to the outputs of the first and second registrars, the outputs of the first register are connected to the inputs of the second adder, the outputs of the second register are connected to the inputs of the first adder, the inputs of the first and second registers are connected to the outputs of the first and second adders, the output of the device is cf The second input is connected to the output of the pulse generator, and the third input is connected to the output of the control device, the output of the element AND is connected to the control inputs of registers, totalizers and the counter, the outputs of which are connected to the inputs of a digital-to-analog converter The control input of the digital switch is connected to the output of control unit 2J. The disadvantages of such a device are limited functional

OPPORTUNITIES of the device and low speed.

The purpose of the invention is to enhance the functionality and increase speed.

This goal is achieved in that the computational voltage converter into a code containing a comparison unit, the first input of which is connected to the output of a digital-to-analog converter, whose input is connected via a digital switch to the outputs of the first and second registers, the first inputs of the first and second registers are connected to the outputs of the first and the second adders, the control input of the digital switch is connected to the output of the control unit; an analog switch, a scaling amplifier, two shift blocks, a digital crossover a switch, an additional register, an additional adder and a storage device, the analog switch inputs are connected to the device input terminals, the analog switch output is connected via a scaling amplifier to the second input of the comparison unit, the output of which is connected to the first input of the additional register, storage device, first, second and Additional adders, the second inputs of which are connected to the outputs of the first, second and additional registers, respectively, the second output of the first register through the first shift unit is connected to the second input of the second adder and through a digital switch to the second input of the first adder, the second output of the second Io register through the second shift unit and the digital switch connected to the second input of the first sum-, torus, output of the additional register is connected to the second inputs the first and second registers with a digital input of the digital switch, the second input of the additional adder is connected to the output of the operating device, the control inputs of the angled switch, the scale a hand amplifier, registers, shift blocks, a memory device, adders and a digital switch are connected to the outputs of the control device, the input of which is connected to the digital input bus of the device.

The drawing shows the structural electrical circuit of the proposed device.

The computational voltage-to-code converter contains analog switch 1, scaling amplifier 2, comparison block 3, digital-to-analog converter 4, control block 5, registers 6-8, adders 9-11, shift block 12, 13, memory 14, digital switch 15 , digital switch 16, input terminals 17 of the device and bus 18 of the digital input of the device.

The computational voltage-to-code converter works as follows.

The translation of the computational voltage converter circuit into a code into the formation of certain dependencies is carried out according to the signals supplied to the digital input bus 18 of the device. These modes correspond to the control signals at the outputs of block 5, which determine the sequence of operation in time of various converter circuits.

According to the signal of block 5, the converted voltage U by the analog switch 1 is transmitted through the scaling amplifier 2 to the input of block 3. The transfer coefficient of the scaling amplifier 2 Km depends on the mode of the generated functional dependence. Converting voltage into a code with a variable transfer coefficient K of scaling amplifier 2 and using alternating + 1 allows the device to compensate the scale change of values and the resulting values without scaling using simple circuit elements.

In the first equilibration cycle, registers 6-8 are entered into the values of computational quantities. Further, the signal from block 5 transfers the code through digital KONMyTaTop 15 to the inputs of digital-to-analog converter 4, the output of which produces the corresponding counterbalancing voltage. Block 3 generates a signal of the result of the convertible and balancing stresses, which is fed to the inputs of adders 9-11 to control the calculation. At the same time, in the adders 9, 10, one calculation step is performed and the new values of the calculation variables are recorded in the registers 6-7. At this, the code balancing and code generation stage ends.

In the second cycle, by the signal of the cycle number and the indication of the operation from the memory 14 to the input

adder 11 transmits a constant which, depending on the result of the comparison, is added to or subtracted from the first code in adder 11. The resulting corrected code is entered in register 8 and transmitted through digital switch 15 to the inputs of digital-to-analog converter 4 to generate the next balancing voltage. In block 3, a new comparison is made.

Claims (2)

conversion and balancing stresses and is generated with the result of the comparison. Simultaneously, in adders 9 and 10, the values are calculated, which are then recorded in registers 6, 7. The considered steps of balancing the transformed voltage and calculating the values of X and Y are repeated n times, after which a register is generated in register 8. Convertible voltage codes in registers 6.7 are functionally associated with convertible voltage Ux. A computational voltage converter into a code has wider functionality and greater speed than the known ones. This effect is achieved using typical, uncomplicated circuit nodes. As a result, this allows the formation of codes / functionally related by Q transformable stresses of direct and convertible trigonometric, hyperbolic and exponential dependencies, and the execution of coordinate transformation operations. The invention Computing voltage converter in the code containing the comparison unit, the first input of which is connected to the output of a digital-to-analog converter, the inputs of which through a digital switch are connected to the outputs of the first and second registers, the first inputs of the first and second registers The control input of the digital switch is connected to the output of the control unit, characterized in that, in order to expand the functionality of the device, to increase its speed, it is An analog switch, a scaling amplifier, two shift blocks, a digital switch, an additional register, an additional adder and a memory device are given, the analog switch inputs are connected to the device input terminals, the analog switch output is connected to a second comparator input, the output of which is connected to the first input of an additional register, the memory device, the first, second and additional adders, the second inputs of which are connected to the first th output of the first, second and additional registers, respectively, the second output of the first register through the first shift unit is connected to the second input of the second adder and through a digital switch with the second input of the first adder, the second output of the second register through the second shift block and digital switch connected to the second input of adder, the output of the additional register is connected to the second inputs of the first and second registers and to the digital input of the digital switch, the second input of the additional adder with The control inputs of the analog switch, scaling amplifier, registers, shift blocks, memory, accumulators and digital switch are connected to the output of the control device whose input is connected to the digital input bus of the device. Sources of information taken into account in the examination 1. US patent 3976869, cl. 235/189, 1976. 2. USSR author's certificate number 588626, cl. H 03 K 13/02, 1978 (prototype).