SU1495993A1 - Analog-to-digital converter - Google Patents

Abstract

The invention relates to the field of digital measuring and computing technology and can be used to convert analog values to digital ones. The goal is to improve the accuracy of conversion in a wide temperature range. The analog-to-digital converter contains an analog input bus 1, a temperature to voltage converter 2, a reference voltage source 3, a resistive voltage divider block 4, an analog switch 5, a voltage follower 6, a controlled scale voltage-current converter 7, on analog switch 8 and scale resistors 9.1-9k, shift register 10, auxiliary converter 11 code-current register 12 successive approximations, current comparison unit 13, performed on current-voltage converter 14 and comp 15 voltage arator, main code-current converter 16, performed on higher-order code-current converter 17, lower-order code-current converter 18 and resistive current divider 19, flip-flop 20, output register 21, computational-control unit 22 , information output bus 23. A feature of the device is the exclusion from the result of the conversion of the temperature component of the nonlinearity error of the main code-current converter 16, additive and multiplicative errors of the analog switch 5, repeater 6 for example Power, controlled voltage-current scale converter 7 and current comparison unit 13. 3 hp f-ly, 2 ill.

Description

on analog switch 8 and large-scale resistors 9.1-9.K, shift register 10, auxiliary converter 11 code-current, register 12 successive approximations, block 13 compare currents, performed on converter 14 current-voltage and comparator 15 voltages the primary transducer is 16 code — current, executed — and the transducer 17 code is the high-order current, the 18-code transducer is the lower-order current and the resistive current divider 19, trigger 20,

15

1495993.1

output register 21, computational control unit 22, information output bus 23. A feature of the device is the exclusion from the result of the temperature component conversion of the nonlinearity error of the main converter 16 code - current, additive and multiplicative errors of the analog switch 5, voltage follower 6, control of the variable voltage converter 7 being the current and the current comparison unit 13. 3 hp f-ly, 2 ill.

equal block 22, information output bus 23. A special feature of the device is the exclusion of the nonlinearity error of the main converter 16 code - current, additive and multiplicative errors of the analog switch 5, voltage follower 6, controlled large-scale converter 7 voltage from the result of the conversion. - current and unit 13 comparison of currents. 3 hp f-ly, 2 ill.

The invention relates to digital measuring and computing techniques and can be used to convert analog values to digital.

The purpose of the invention is to improve the accuracy of the conversion in a wide temperature range.

I FIG. 1 is functional; Analog-to-digital areobrazu- 1tel; in fig. 2 - functional scheme of the computing and control unit.

The analog-to-digital converter (Fig. 1) contains an analog input bus 1, a temperature-to-voltage converter 2, a reference voltage source 3, a resistive voltage dividers 4, an analog switch; 5, a voltage follower 6, control scalable converter 7 voltage - current, made on analog switch 8 and scale resistors 9.1-9. To, shift register H, auxiliary converter 11 code - current, register 12 consecutive approximations, current comparison block 13, run on the converter 14 current - April voltage comparator 15 and voltage, the main converter 16 code - current converter configured to code 17 - MSB current, the inverter 18

the code is the low-order current and the resistive current divider 19, the trigger 20, the output register 21, the computing control unit 22, and the information output bus 23.

The computational control unit 22 (Fig. 2) is executed on the central processor 24, the permanent memory unit 25, the operational memory unit 26, the block

five

0

5 0 j

0

five

ke 27 decryption, the input device 28 and the block 29 stop-start performed on the D-trigger.

The main transducer 16 code - current is made on the basis of a redundant measuring code.

In the proposed converter in the permanent memory unit 25, only the weights of the uncorrectable bits, whose time drift can be neglected, are brought in. The codes corresponding to them occupy a small amount of memory. In the manufacture of the converter, measurements will be required only at three temperature points (at normal temperature, maximum and minimum). When the converter operates at temperatures other than the measured ones, the computational control unit calculates the values of the parameters of interest using interpolation methods.

This approach allows the use of a non-temperature-controlled source 3 of the reference voltage and a block 4 of resistive voltage dividers, the output values of which are measured at three temperature points during the manufacturing process, recorded in the fixed memory unit 25 and used in the calculation of direct conversion process.

A feature of the converter is the exclusion from the result of the temperature component conversion of the nonlinearity errors of the main converter 16 code - current, additive and multiplicative errors of analog switch 5, voltage follower 6, controlled voltage scale converter 7 - current and current comparison unit 13. Moreover, the correction of the 1 H 1 dependences of real weights for a group of exact discharges and values of the reference voltages is performed using the interpolation method. Thus, it is practically expedient to interpolate the values of a function by some) G n. ---- iHtlt2b .. (t-tj-,) (t-tjvo ... (t-tK)

 (,) (t.-tj ..) (t- t7Tr: :(

where t, U (t) is the current temperature and the corresponding voltage;

temperature and voltage values at the j-th interpolation node;

k is the number of interpolation nodes.

At the stage of manufacture of the converter, the block 25 of the memory of the computational control unit 22 is loaded with codes corresponding to the weights of precise distances measured by the exemplary tool at different temperatures (for example, at normal, minimum and maximum temperatures), as well as

codes

K1,

TO,

onj onj, ... Konj 9 corresponding, the reference stresses L | ,. , AOP, ... Hell source 3 of the reference voltage and block 4 resistive voltage dividers. When determining the current value of the codes corresponding to the weights of the exact bits or codes of the corresponding reference voltages, the converter encodes the output voltage of the converter 2 temperature - voltage and in accordance with (1) organizes the computational algorithm. In the following, the codes thus obtained are used to correct the linearity of the main transform, the code current and correct the multiplicative component of the transform. At the same time, additional error due to an inaccurate determination of the code corresponding to the output voltage of the converter 2 temperature - voltage does not occur, since its required temperature sensitivity is low.

The proposed converter allows encoding of both high and low levels of the input signal with high accuracy. At the same time, from the result of the conversion to the historical number of experimentally removed points (interpolation nodes). In this case, using, for example, the Lagrange interpolation method, the desired function U (t), with any given accuracy, can be represented as a polynomial

five

0

five

0

five

0

five

0

five

The errors of the analog switch 5, the voltage follower 6, the current-voltage converter 7 are included, and the current comparison unit 13 due to the fact that the blocks listed are covered by the digital correction circuit. The absolute and relative temperature errors of the scale resistors 9 are corrected with the help of the source 3 of the reference voltage and the block 4 of resistive voltage dividers.

At the same time, the resistors of the block 4 of resistive voltage dividers are microelectrically designed, the absolute drift of which is 1–1.5, more than relative. Therefore, their relative tag-drift drift can be neglected.

The converter operates in two modes: self-verification and direct conversion;

The self-test mode consists of four cycles.

In the first cycle, a code is determined that corresponds to the ambient temperature. To do this, using an analog switch 5, the output of the converter 2 temperature - voltage is connected to the input of the voltage follower 6 and encoding occurs. The result of the encoding is the code of the desired temperature, which is recorded in the memory block. In the second self-test cycle, the non-linearity error is eliminated. To do this, the codes of the deviations of the weights of the bits of the code converter 17 are determined - the current of the higher bits from the required values without taking into account the slope of the coding characteristic.

The codes for the deviations of the weights of the bits are also determined, taking into account the ambient temperature and using the Lagrange interpolation method.

Using an analog switch 5 5 to the input of the repeater 6 voltage under- 1 |: the bus of zero potential is switched on, the auxiliary converter 11 sjcofl - current forms the auxiliary analog value Ag. Each value of the analog value And g ,. twice balanced by the method of discharging the bits by coding the bits of the main converter 16 code - current, once with the prohibition of the inclusion of the turned 1 azr daz another time without the prohibition. When the results of each of the two

N,.,

ten

where a p is the i-ro digit of the equilibrium result code when encoding with the A signal.

The loop ends with writing the offset code to the memory pool.

In the fourth self-test cycle, the multiplicative (scale error) conversion error is determined and eliminated.

In the operation of transformations and. to the 1st bit of form-15 ° - the switch is switched to 1. 1. In the register 12, the serial-switching switches 5 and 8 are connected as an approximation. As the K g code is formed, its binary equivalent K p is formed using 1 computational control of a second block 22 20

alternately through a repeater 6, the voltage of the reference voltage A.,, ... dadg, to the large-scale resistors 9.19.,

op j

Next comes the coding of each of the reference voltages. As the balancing result code is generated in the sequential approximation register 12, the scale code K is generated in the computing control unit 22 by the formula

but the formula is

to g, g ,.

de a - the digit of the 1st digit of the K code of the first equilibration result;

I NJ. - the binary equivalent of i-ro

I bit

For code K g it is also formed

The binary equivalent of the formula

, -ia; .N .. (2)

ihfte is the i-ro digit of the K code.

.As in the expression (2) codes NJ zero for i, n-m + 1 (the contents

memory flock is zero), then the code K pa-35 receiving code) occurs de45

The yen code for the real weight of the 1st bit () and is written into memory block 26.

Similarly, the determination of codes of real weights of the base 40 inaccurate bits taking into account the previously defined codes K f.

The second cycle ends with the determination of the codes of the real weights of all m. Non-current bits.

During further work in the self-test mode, the determination of additive (error zero) and multiplicative (scale error) transformation errors occur,

In the third cycle of self-calibration, the offset determination of the zero offset of the entire converter proceeds. At the same time, the zero potential bus is connected to the input of the follower 6 of the voltage and encoding occurs, during which I build the binary equivalent of the “code K according to the formula

R . f tion of code K (t) on code K

ch

as a result of the division, a scale factor code K is generated, on which all real weights of inaccurate bits defined in the second cycle and stored in memory block 26 of the computational control unit are multiplied.

Thus, the codes of real weights of inaccurate inquiries are determined taking into account the slope of the coding characteristic of the fordule

TO

m „

to „„ - K

wg pe

The cycle ends with writing all Kpj codes to the memory block, where they are stored until the next calibration cycle.

In the direct conversion mode, the input analog signal is level dependent via analogue switches 5 and 8; one

N,.,

where a p is the i-ro digit of the equilibrium result code when encoding with the A signal.

The loop ends with writing the offset code to the memory pool.

In the fourth self-test cycle, the multiplicative (scale error) conversion error is determined and eliminated.

During the operation of the conversion °, the switchboard switches 5 and 8 are switched,

alternately through a repeater 6, the voltage of the reference voltage A.,, ... dadg, to the large-scale resistors 9.19.,

op j

Next comes the coding of each of the reference voltages. As the balancing result code is generated in the sequential approximation register 12, the scale code K is generated in the computing control unit 22 by the formula

K. Za.N.-K

Ml

where a.

., - digit of the 1st digit of the code

the result of balancing,, 2, ..., K.

Then, in the computational control unit 22, the code (t) is calculated using relation (1). After

R . f tion of code K (t) on code K

ch

in re

As a result of the division, the code of the scale factor K is formed, into which all codes of real weights of inaccurate bits defined in the second cycle and stored in memory block 26 of the computational control block are multiplied.

Thus, the codes of real weights of inaccurate inquiries are determined taking into account the slope of the coding characteristic of the fordule

TO

m „

to „„ - K

wg pe

The cycle ends with writing all Kpj codes to the memory block, where they are stored until the next calibration cycle.

In the direct conversion mode, the input analog signal, depending on the level, through analog switches 5 and 8 is fed to the output of one of the large-scale resistors 9 and is converted into a working code Krcd using a bit-coded method. In parallel with the formation of the K code, the slave in the computational junction-correction unit 22, the output binary code is formed taking into account the codes of real weights,: corrected in scale, and the zero offset code obtained in the self-calibration mode. The adjusted output code is calculated by the formula

TO

8M)

 G a; N (+ Ko.

Then the code K d ,, is rewritten into the | | Running register 21 and by the control signal the end of the conversion can be read from the output bus 23. This completes the direct conversion.

Claims (4)

1. An analog-to-digital converter containing an analog switch, the first information input of which is an input analog bus, the first control input is connected to the first output of the computing and control unit, the first and second inputs of which are the Start and input buses Reset, the second output is connected to the first control input of the shift register, the information outputs of which are connected to the corresponding inputs of the auxiliary code-current converter, the second control input is connected to the third The output of the computational control unit, the fourth output of which is connected to the control input of the sequential approximation register, the fifth outputs are connected to the corresponding information inputs of the output register, whose outputs are the output information bus, the control input is connected to the sixth output of the computational control unit, the third input of which is combined with the information input of the register of successive approximations of 5 n outputs of which are connected to the corresponding inputs of the n-bit main th code converters - current formed on the basis of measuring the excess code, the output of which is connected to the first input of comparing the current block. 0 five 0 five 0 five 0 five 0 five I differ from that, in order to increase the accuracy of the conversion in a wide temperature range, a temperature converter is introduced into the voltage, a reference voltage source, a voltage follower, a controlled voltage scale converter - current, a trigger, a resistive block voltage dividers, made on K series-connected resistors, the second terminals of the first and K-th resistors of which are connected respectively to the output of the reference voltage source and to the width of zero potential, the second output of the first the resistors and the first terminals of the remaining K-1 resistors are connected to the corresponding inputs of the first to the K-th group of information inputs of the analog switch, the second information input of which is connected to the output of the temperature to voltage converter, the third information input is connected to the zero potential bus, the second control the input is connected to the first control input of the controlled scale voltage converter - current and is connected to the second output of the computing and control unit, the output of the analog switch via a voltage follower connected to the information input of a controlled scale converter voltage - current, the second control input of which is connected to the seventh output of the computing and control unit, the output connected to the second input of the current comparison unit, the third input of which is connected to the output of the auxiliary converter code - current, output - to the information input of the trigger, the first and second control inputs of which are connected respectively to the fourth and eighth outputs of the computing and control The unit, the third input of which is connected to the trigger output, the ninth output is the bus Ending conversion, and the fourth input is connected to the (n + 1) -th output of the serial approximation register. 2. The converter according to claim 1, which is based on the fact that the controlled scale voltage converter is a current made on the analog switch and the scale resistors, the first terminals of which are combined and are the output of the controlled switch. scale converter - current, the second terminals are connected to the corresponding outputs of the analog switch, the first and second control are: l inputs and information input, which are respectively the first and second control inputs and: the information input of a controlled scale converter; - ni - current. 3. The converter according to claim 1, t - | characterized by the current comparison block made on the voltage comparator and the current – voltage converter; the iKOTOporo current summation input is the first, second and: third block inputs, the output is | If the first input of a voltage comparator, the second input of which is connected to the zero potential bus, the output is the output of the block. I 4. The converter according to claim 1, t - is verified by the fact that the computational-control unit is made 1 on the central processor, the block of the PERMANENT memory, the RAM, the decryption unit, the input device, the stop-start unit performed on the D-flip-flop, the JKOToporo S-input is the first input of the block, the D-input is connected to the zero-potential bus, the output is the ninth output of the block and connected to the Ready input of the central processor, whose Reset input is the second input of the block address outputs are connected to the corresponding addresses. to the inputs of the fixed memory unit and the RAM unit and to the inputs of the decryption unit, the information inputs-outputs are connected to the corresponding information outputs of the fixed memory unit, the information inputs-outputs of the RAM unit, the outputs of the input device and are the fifth the output of the block, the output Vshchacha is connected to the input of the record-schichit of the RAM block, the input of the resolution of which is connected to the first output of the decryption unit, the second output of which is connected to the input of the resolution of the operation of the block the third to ninth outputs are the outputs of the block from the first to the fourth and sixth to the eighth, the tenth output is connected to the input permit of the input device, the eleventh output is connected to the clock input of the D-flip-flop, the information input of the input device is the third input of the block, and the control input of the input device the fourth input of the block. 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