SU953721A2 - Digital analog converter - Google Patents

Description

(5) DIGITAL-ANALOG CONVERTER

The invention relates to digital measuring and computing technology and can be used in information measuring systems for converting digital codes with irrational bases into analog values. According to the main author. St. If is known a digital-to-analog converter (DAC) containing a register, a reference value block, a block of key elements, a difference difference block, a device for summing standards, a control block, a code scanner, a convolution block, a block of logic elements, and a digital commutator The DAC input is connected to the first register input, the output of which is connected to the first input of the scanner of the code and the first input of the digital switch, the output of which is connected to the first input of the block of key elements, the second input of which is connected n to the output of the unit is FLASH values, and the output is with the input of the device for summing up the standards, the output of which is connected to the first output bus of the DAC and to the input of the difference separation unit, the first output of the scanner of the code is connected to the second input of the digital switch and the first input of the logic elements, the second the output to the first input of the convolution unit of the code, the output of which is connected to the second input of the block of logic elements, the output of which is connected to the second output bus of the D / A converter, the output of the difference difference allocator is connected to the input of the control unit and, five outputs of which are connected respectively to the second inputs of the register, scanners and convolution, codes, as well as to the third inputs of the digital switch and the block of logic elements PJ. A disadvantage of the known device is the limited accuracy of the code-to-analog conversion due to temperature and time instability arising in a resistive voltage suppressor, which is used in a block of reference values. Information about the magnitude of the error code in a known device does not allow an increase in the accuracy of the conversion. The purpose of the invention is to improve the accuracy of the conversion. The goal is achieved by the fact that a minimum error code selection block, an error register block and an error block are entered into the digital-analog converter, the first input of which is connected to the second output of the code scanner, the second input - with the output of the error registers, the output by the vertical input of the logic block, and the third input with the sixth output of the control block, the second input of which is connected to the output of the logic block and the first inputs of the error register block and the selector block second error code, the second inputs of which are connected respectively to the seventh and eighth outputs of the control unit, and the output of the minimum error code selection block is connected to the third input of the code convolution unit. The drawing shows the functional diagram of the DAC. It contains input 1 of the converter, register 2, scanner code 3 digital switch 4, block of key elements 5 block of reference values 6, device for summing reference values 7 first output 8 of the digital-analog converter, block for selecting the minimum error code 9 difference difference block 10, logic block 11, code 12 convolution block, error selection block 13, block of error registers 14, control block 15 second output 16 of the D / A converter. Input 1 of the digital-to-analog converter information, through which the first input of register 2 receives a digital code. The output of register 2 is connected simultaneously with the first inputs of digital switch k, the scanning unit of code 3. The output of digital switch t is connected to the control input of the block of key elements 5, the information inputs of block 5 are connected to the output of reference values block 6. The input of summation device of reference values 7 is connected with the output of the key element block 5; The output of block 7 is the first output 8 of the D / A converter, on which the resulting analog signal of the code-analog converter process is formed. The output of the difference difference block 10 is connected to the output of the summation device of reference values 7- In the metrological control mode, the difference difference block 1, a comparison of the previous and subsequent analog signals formed at the first output B of the digital-analog converter, is made. The output of block 10 is control and connected to the first input of control block 15. The first output of the scanner of code 3 is connected simultaneously to the second input of the digital switch k and the first input of the block of logic elements 11. The second output of the scanner of code 3 is connected to the first input of the convolution unit code 12 and the first input of the error sampling block 13; The convolution blocks 12 and the sweep of code 3 perform a logical sweep and convolution operation of code combinations. The output of block 12 is connected to the second input of the block, logic elements 11 and the fourth input of the digital switch. The output of the logic element block 11 is the second output 16 of the D / A converter, which is simultaneously connected to the first inputs of the minimum error code selection block 9, the error register block and the second input of the control unit 15. The third input of the convolution unit of the code 12 is connected to the output of the minimum error code selection block 9 The block for selecting the minimum error code 9 performs a logical comparison operation and from a certain number of code combinations makes the selection of the minimum code combination itself, fixing at the same time the number e e admission. The output of the error register block I is connected to the second input of the error sampling block 13. The error register block 14 serves to store and transmit the error codes of the DAC bits. The output of block 13 is connected to the fourth input by a block of logic elements 11 that performs the operations of addition and subtraction of code combinations. Error sampling device 13 is used to sample from block T in accordance with the position numbers of the error code bits of these bits. The first, second, third, fourth, fifth, sixth, seventh and eighth outputs of the control unit 15 are connected respectively to the second input of the register 2, to the third input of the digital switch k, to the second input of the scanner code 3, to the second input of the convolution block 12 , with the third input of the block of logic elements 11, with the third input of the sampling block of error 13, with the second input of the block of error registers 1, with the second input of the block of selection of the minimum error code 9. The control unit 13 ensures the operation of the device. The DAC operates in two modes: meteorological control of the linearity of the output characteristic and the mode of direct conversion of the input digital code into an analog value. In the mode of metrological control of the output characteristic, all blocks of the proposed device participate except for block 9 and in the mode of direct conversion it does not participate in the formation of the signal at output 8 of the difference selection block 10. In the process of the metrological control of the linearity of the output characteristic, the value of weights is determined bits from the required values and their registration. Codes with irrational bases include Fibonacci p-codes and golden P-proportion codes. in the code of the golden p-proportion, any real number Z can be represented as i, where Ea is a binary number; Yr is the weight of the 1st bit; p is a code parameter (0, 1,2, 3. ... V.) To determine the weight of the 1 st bit for various code parameters, it is necessary to solve the equation xP -xP-I O, (2) which is the characteristic equation of a polynomial ( 1). The ratio of neighboring p-numbers of Fibinacci for large numbers is also approximated by a cobra. A characteristic feature of these codes is the ambiguity of the representation of digital information, i.e. a single number of resulting numbers can be assigned according to a certain number of different code combinations. For p-codes there is only minimal pho The representation of the numerical value, i.e., after each significant unit in the code combination, is followed by at least p-zeros. The transition from the minimum form to the nominal one is performed using the code scanning operation, which consists in replacing the unit in the 1st bit by one in (1-1) -m and (1-p-1) -th bits. The convolution operation is the inverse sweep operation. These operations do not change the resulting equivalent value represented by the code combination, but change only the form of the representation code combination. This is the ambiguity of the presentation of digital information in these codes. 3 non-mode; Rotational control by equilibrium1:; ieei i-ro of checked discharge by a group of younger bits, provided that () the younger bits satisfy its technical requirements, the formation of the land code (5) of the 1st turnable digit Yes. This error code is fixed at the second output 16 of the DAC. Then, at the command of the control unit 15, the error code i-ro of the turnable bit is written into the block of error registers 1, the number of which corresponds to the position of this bit in the DAC. The formation of the error code (i + 1) -ro bit: is performed in the same way as by balancing this bit with a group of younger bits. The resulting error code is generated at the second output 16 of the D / A converter. If, in the resulting balancing code combination, there are bits that already have error codes stored in the error register block 15, then in block 13, the data from the error codes, starting with the highest numbers, is performed alternately. Data error codes through the block 13 is fed to the fourth input of the block of logic elements 11.

To determine the magnitude of the error code (i + l) -ro of a bit, it is necessary to add the error codes of the lower order bits, which have formed a balancing code combination for the given bit. Consider an example. Take two code combinations

i + 1 i i-1 1-2 i-3 f- i-5, ... i-n N;, - 000000 0 N (j - 0 1 0 1 1 -0 0 / .... ,, 1

The basic mathematical relationship for balancing the (i-l) -ro bit of a turnable is an expression of the form

Ni., Ny, (3)

(this equation is typical for the ideal case)

where is a code combination containing only one unit of the 3 (i 1) -th bit; NU code combination, balancing (I1) -th bit.

If the resistive voltage divider has an error, then the following condition is true

Nj ,, (k)

where AN is the error (i + 1) -ro

bit;

LuNu is the total error of the balancing bits.

From the expression (k) we define the error (t - (- l) -ro bit and DAC

uN, iiN4. (five)

j; - j

Thus, on the basis of expression (5), we see that to determine the error of the (i + 1) -th bit, it is necessary to perform the summation of errors in the block of logic elements 11 taking into account their signs.

The determination, computation, and recording of the error codes of the calibrated high-order bits are performed similarly.

After the error code of the most significant bit of the D / A converter is fixed, the process of metrological control ends.

The ambiguity in the presentation of digital information in the proposed device allows to obtain a fixed set of code combinations, the resulting errors of which have different values and signs. WITH

with the help of the 1 / {th sweep, we can stop on the code combination having the minimum error of the division factor. This property is the basis for improving the accuracy of code-equivalent conversion. 8 in the conversion mode, the input code combination through input 1 of the D / A converter arrives at the first input of register 2. From the output of register 2, this code combination enters the first input of the scan code 3 blog, then from its output it goes to the first input of the error sampling block 13. At the command of the control unit 15, control signals are sent to the error register block 1 and block 11. As a result, from the error register block 1, the error sampling block 13, to the fourth input of the logic element block 11, receives in a certain order the error codes of the bits involved in this code pattern. After performing the arithmetic operation of adding the error codes of the original code combination in block 11, the error code of the original code combination will be generated at the second output 16 of the D / A converter. This error code is fed to the first input of block 9 and its arrival number is also recorded. At the command of the control unit 15 in the scanner unit of code 3, the first cycle of the scanning operation is performed. This code combination is fed to the first input of an error sampling block.

13, sampling the corresponding error codes from the error register block. From the output of the error sampling block 13, these error codes are input to the block 11. Block 11 performs the addition of the error code data and the error code of the original code combination is generated at the second output 16 of the D / A converter after the first clock sweep operation is executed. block 9 with its next number.

Subsequent sweeps of the sweep operations are performed in a similar way, and in this case, in block 9, error codes are fixed on the given code combinations. At the command of the control unit 15 in block 9 choice

the minimum error code determines the minimum error code, and also determines the sweep number of the original code combination. On the control signal of the control unit 15 into the code convolution unit 12, the operation of convolving the code to a codeword having a minimum error is performed. The number of convolutions of the unwrapped code combination of the initial one is determined by the control signal from block 9 for selecting the minimum error code by a fixed number of the minimum error code. From the output of block 12, the generated code combination with minimum error through digital switch k enters the control inputs of the block of key elements 5, which connect from the block of reference values 6 through the information inputs of the block of key elements 3 to the input of the device 7 summation of reference values analog values. As a result, the resulting analogue signal will be formed at the first output 8 of the DAC with the minimum error.

Claims (1)

1. USSR author's certificate (Г 9 (, кл. И 03 К 13/02, 17.12.79. / VV / Yu / V