SU1343428A1 - Device for reproducing functions of two variables - Google Patents

Abstract

This invention relates to automation and computing. The aim of the invention is to improve the accuracy of the functional transformation. The device contains two analog-digital converters 1 and 2, a memory block 3, eight multiplying digital-analog converters 4, 5, 10, 11, 14, 15, 16 and 17, two digital-analog converters 8 and 9, five adders 6, 7, 12, 13 and 19, reversible counter 18. Compared with the functional transformation based on the principle of piecewise linear approximation in one variable and piecewise quadratic in the other, the device implements piecewise quadratic approximation in two variables at the same time, which allows to increase the accuracy of the function conversion. 2 Il. c (L f (n.y)

Description

113

The invention relates to analog and analog-to-digital (hybrid) computing technology and can be applied in the simulation of automatic control systems.

 The aim of the invention is to improve the accuracy of the functional transformation.

FIG. 1 shows a block diagram of a device for reproducing functions of two variables; in fig. 2 - an example of piecewise quadratic approximation of a function of two variables

The device for reproducing the functions of two variables contains two analog-to-digital converters (ADC) 1 and 2, memory block 3, the first 4 and second 5 multiplying digital-analog converters (DAC), the first 6 and the second 7 adders, the first 8 and the second 9 DACs, third 10 and fourth 11 multiplying DACs, third 12 and fourth 13 adders, from the fifth to the eighth multiplying DACs 14-17 ,, reversible counter 18 and fifth adder.19.

The device works as follows.

The reproduction area of a given function of two variables z F (x, y) is divided into equal parts. It is assumed that i is the number of the function representation interval with respect to the variable x; j is the interval number by variable y. The one shown in FIG. 2, the ijth part of the partition of the function is bounded by four approximating parabolas. Each parabola is drawn through three points, two of which are function setting points, and the third point has two zero coordinates and lies on the x or y axis.

For example, parabola I is drawn through points with coordinates (O, y:, 0),

Hij)

(x ,, yj, zjj), (X; ,, i l,

The equation of a parabola drawn through the indicated points has the form q) (x, y) w, x F (x; ,, yj) -Xj, F (x;, yi) Jx + ra ,; X;, F (x;, yj)

-x; F (xj ,,, yj) x%

1. where t „-j-; r

X. „L„ v-.V

(one

.

- x-xf,

By analogy, the equation of parabola II

passing through points (O, y (x ;, Y: „, Zj.,), (x; ,, y

J +

) ti has the form

0),),

1t (r

H, yj-c) W x x F (X ;, y ;,)

g + i

- (x ;, у- ,,) X 4- m, x,., F (x ;, y.Ui) - x; F (x ,,, yj.M) jx2

 iU

(2)

The entire approximating surface on the ij-M plot can be represented as a set of parabolas for any value on this plot, each of which is drawn through points lying on parabolas I and II and its corresponding point 0.

The equation of the approximating surface on the ij-M segment has the form C () (x, y) mc, y ((x, yv,) Q f -

Y) m V (x, .y,) y + ha

W; V (x, yj ,,) 1y

DU, H, ((x.Jj)

5 0 5

about

one

where t.ts --5

7 V V - V V,

d J j JflY r

In memory block 3, the previously calculated coefficients are written to reproduce the functions V (x, yj,) and m.yj, (j) (x, y), which are functions of the variable x. Since the approximating parabolas were drawn through the zero point, for both functions it is required to store four coefficients of each segment. Relation (1) is implemented by a circuit consisting of multiplying DACs 4 and 14, DAC 8, adder 6. Relation (2) is realized by multiplying DACs 5 and 15, DAC 9, adder 7. Voltages corresponding to ni-tjyj +, V (x, y |) and v (x., Y,. „).

five

are removed respectively from the converters 14 and 15. The coefficient of the relation (3) is realized at the output of the adder 19.

To obtain the coefficient of y in the expression (3), a reversible counter 18 is used, multiplying the DACs 14 to 15 and the adder 12.

The voltage corresponding to the value of y, -, is removed from the k high-order bits of the output of the second ADC. The value of k is determined from the ratio 2 p, rc n the number of splitting intervals along the y axis.

0

I

Voltage corresponding to

cheniyu W;

1 + 1

removed from the output of rever50

55

sive counter 18, which is built on a scaling scheme with a conversion factor of one. As such a counter, for example, a standard chip E155IE7 four-bit reversible counter, built on the basis of T-flip-flops, with which 14 and 15 outputs are combined, can be used. To the counting input of such a counter, (k + 1) -A is applied.

bit output of the second ADC. The outputs of the multiplying DACs 14 and 15 implement the values of uU, x Klf (x, yj) and y (x, yj,), respectively, which are fed to the inputs of the adder 19.

The voltage corresponding to the value of tf (x, y) is removed from the output of the converter 17.

Thus, in the proposed device, in comparison with the reproduction of functions based on the principle of piecewise linear approximation in one variable and piecewise quadratic in another, the accuracy of the functional transformation is improved by using piecewise quadratic approximation in both variables.

The error in reproducing a number of frequently occurring functions, for example, power functions of the form z (x + + y), does not exceed 0.1–0.2% at eight split intervals along the x axis and y axis.

Claims (1)

Invention Formula A device for playing two-variable functions, containing a first analog-to-digital converter connected by an input to the first information input of the device and analog inputs of the first and second multiplying digital-to-analog converters, and high-order outputs to the first group of address inputs of a memory block connected by a second group of address inputs with outputs 45 older bits of the second analog-to-digit. a digital-to-analog converter connected to the second information input of the device; the first output of the memory unit is connected to the digital input of the first multiplying analog-digital converter connected by the output to the first input of the first adder connected to the second input of the first digital-analog converter, connected by a digital input to the second output of the memory unit, and an analog input - to the input voltage bus and analog input of the second digital channel A second converter connected by a digital input to the third output of the memory unit, and an output to the first input of the first adder is connected50 55 l, connected by digital inputs with outputs k) of the higher bits of the second analog-to-digital converter, and output with the second input of the third adder connected by output to the second input of the fourth adder whose output is connected to the analog input of the eighth multiplying analog-analog converter connected by digital inputs to the outputs of the bits of the second analog-to-digital converter and the digital inputs of the fourth multiplying digital-to-analog converter, and the output to the output of the device, with the output of About the adder is connected to the analog input of the fourth multiplying digital-to-analog converter. A second input to the output of the second multiplying digital-to-analog converter, the digital input of which is connected to the fourth output of the memory block, and the outputs of the third and fourth multiplying digital-to-analog converters are connected to the first inputs of the third and fourth sum of 0 tori, respectively, in order to improve the accuracy functional transformation, it additionally introduced the fifth adder, with the fifth to 5 eighth multiplying digital-analogue converters and reversible counter connected by a counting input to the output of the (n-k) th bit of the second analog-to-digital converter (where 0 n - the size of the second analog-to-digital converter, k - the number of bits of the second group of address inputs of the memory unit, and the outputs of the bits - with digital inputs of the third 5 multiplying digital-to-analog converter connected by analog. input to the first input of the fifth adder and the output of the fifth multiplying digital-to-analog converter connected by an analog input to the output of the first adder, and digital inputs to the outputs of the bits of the first analog-digital converter and digital inputs of the sixth multiplying digital-analog converter connected by an analog input with the output the second adder, and the output - with the second input of the n adder and the analogue input of the seventh, ippozhayayu5 45 . digital-to-analog converter 50 55 l, connected by digital inputs with outputs k) of the higher bits of the second analog-digital converter and the output with the second input of the third adder connected by output to the second input of the fourth adder, the output of which is connected to the analog input of the eighth multiplying digital-analog converter connected by digital inputs to the outputs bits of the second analog-to-digital converter and digital inputs of the fourth multiplying digital-to-analog converter, and the output to the output of the device, with the output of an adder coupled to the input of the fourth analog multiplying digital-to-analog converter. 2