SU1732471A1 - Parallel-to-series n-digit analog-to-digital converter with automatic correction of conversion function - Google Patents

Abstract

The invention relates to information and measurement technology. The invention makes it possible to increase the accuracy of the conversion by providing analogue correction of the results generated in the first conversion step, which allows the use of a fast-acting and highly stable but non-precision DAC. The correction is made with respect to a precision adjustable voltage source 7, the accuracy of which determines the accuracy of the entire device. This is achieved in that a device containing k-bit analog-to-digital converter 1, digital-to-analog converters 4, 11, memory 12, subtractive amplifier 5, adder 8, reversible counter 13, multiplexer 15, register 2, block 3 control, switch 9, switch 10 is entered, register 2, code comparison block 14, 1 hp ff, 2 Il. fiCH n SP with VJ from th VI

Description

The invention relates to information and measurement technology.

The purpose of the invention is to increase speed.

FIG. 1 shows a functional diagram of the converter; in fig. 2 - functional block diagram.

The converter (Fig. 1) contains a K-bit analog-to-digital converter (ADC) 1, register 2, control unit 3, digital-to-analog converter (DAC) 4, subtractive amplifier 5, input b of unit 3, adjustable voltage source 7, adder 8, switches 9 and 10, digital-to-analog converter 11, memory 12, reversible counter 13, code comparison block 14, multiplexer 15, block 3 has inputs 16-18, output 19, input 20, outputs 21-28.

The control unit 3 (FIG. 2) contains AND elements 29-34, a counter 35, elements OR 36 and 37, a trigger 38, elements 39-42 of a delay, and a counting trigger 43.

The converter operates in two modes: automatic correction mode and in measurement mode.

When a supply voltage is applied at the initial reset signal, which in FIG. 1 and 2 are conventionally not shown, the device is reset, and a pulse signal is generated at the output of the element 42. In the initial state, the device is in the automatic correction mode, while the flip-flops 38 and 43, the counters 13 and 35, the register 2 are reset, and zero cells are set in the cells of the block 12.

The automatic correction mode is intended for precise adjustment of the m most significant bits of the first conversion cycle.

The zero code of the counter 35 at the output of the source 7 establishes a zero voltage UOST. The setting time of the output voltage Uiar is determined by the speed of source 7 and does not affect the speed of the converter in the measurement mode, and its accuracy must be at least the low-order bits of the entire converter.

For the zero signal from the direct output of the trigger 38, the switch 9 connects the converter input to the output of source 7, and for a single signal from the inverse output of the trigger 38 through the element OR 37, the switch 10 connects the input of the A / D converter 1 to the output of the detracting amplifier 5.

In the correction mode, at the output of counter 35, m higher conversion bits are generated, which are fed to the inputs of source 7 and through multiplexer 15 to

the DAC 4 inputs and address inputs of the storage device 12. The reference voltage from the output of the source 7 is supplied through the switch 9 to the input of the subtractive amplifier 5, the other inputs of which receive the compensating and correction voltage generated by the D / A converter 4 and DAC 11. In this case, the transmission coefficient for The input voltage UBx and the signal from the DAC 4 are selected in accordance with the Kper expression. 2n-k

The number of bits I of the corrective DAC 11 is selected in accordance with the expression

I IOQ2

А АЦП- + Д Un / 2n

where A is the errors of the DAC 1 and DAC 4;

n is the number of bits of the output code.

The transmission coefficient for the signal from the DAC 11 is determined by the expression

rm

and

one

on

w -I

where U is the weight of the most significant bit of the adjustable part of the output code.

After a time determined by the installation time of the source 7, DAC 4, DAC 11 and subtractive amplifier 5, the output of element 42 will form the leading edge of a single signal coming through element 36 to the input of Starting A / D converter 1.

At the output of the A / D converter 1, k lower bits of the second conversion cycle are generated. On the Readiness command of the A / D converter 1, the element 41 is started and the output of the 28 of the block 3 generates a signal of the Conversion end, which will allow the correction signals from the block 14 to pass through the block 3 to the reversible counter 13. The block 14, compared the bipolar code k of the lower order bits a bipolar zero-voltage code, it generates difference and equality signals.

Thus, according to the signal of the Conversion end, the output 25 of the block 3 generates a pulse signal allowing writing to the counter 13 a code from the output of the memory 12 at the selected address of the corresponding high-order bits. Simultaneously, the signal 40 ends the conversion. Element 40 starts. The delay is determined by the recording time of the installation inputs of the code in counter 13. The pulse signal from the output of element 40 passes to the summing,

or to the subtracting input of the counter 13 depending on the sign of the difference of the block 14 and starts the element 39. The delay time of the element 39 is determined by the installation time of the counter 13. The pulse signal from the output of the element 39 records the output code of the counter 13 into the memory 12. This code is converted by the DAC 11 to the correction voltage supplied to the subtracting input of the amplifier 5. The corrected voltage from the output of the amplifier 5 through the switch 10 is fed to the input of the ADC 1, which is triggered by a pulse signal cient 41 delay. The duration of the delay signal is determined by the time of setting the voltage at the output of amplifier 5. The result of the conversion from the output of ADC 1 will again go to block 14. In the event that this code does not equal the zero value, the device's operation cycle is repeated until the codes in block 14 are compared. The output of ADC 1 of zero code unit 14 will generate an equality signal, which through elements 29, 30 will go to the counter input of counter 35. According to counter code 35, source 7 will generate the following reference voltage, and the correction process will be The same way is repeated. Thus, in the correction mode, the m high-order bits of the first conversion cycle are precisely tuned. In this case, the correction values of the voltages m of the most significant bits generated by the D / A converter 11 are recorded in the memory 12 at the addresses corresponding to the codes of the reference voltages.

Consider the operation of the device in the measurement mode. This mode starts with the arrival of the Start command. In this case, regardless of the state of the device elements in the correction mode, the trigger 38 will go to one state, and the trigger 43 will go to the zero state and the ADC Start signal will pass through element 36 to ADC 1. A single signal from the direct output of the trigger 38 switches the switch 9 from the output of source 7 to the device input, and the multiplexer 15 from the output of counter 35 to the output of register 2 and resets the counter 35 to the zero state, and a zero signal from the inverse output will block the passage of recording signals into the counter 13 and the storage device 12, blocking the element 34. The zero signal from the direct output of the trigger 43 through the element 37 will switch the device to the first conversion cycle, switching the input of the A / D converter 1 from the output of the amplifier 5 to the output of the switch 9, allow entry to the register

2 and blocks the passage of the Readiness signal of the A / D converter through element 33 to the output of the Conversion end.

At the output of the k-bit ADC 1, m higher bits of the first conversion cycle are written to register 2. Upon the completion of the conversion, the Readiness signal of the A / D converter 1 is generated, which translates the trigger 43 into the unit state 0, which corresponds to the transition of the device to the second conversion cycle. On a single signal from the direct output of the trigger 43, the register 2 switches to the storage mode, the element 33 is unlocked, the input of the A / D converter 1 through

5, the switch 10 switches to the output of the amplifier 5, and the delay element 41 is started. The input voltage of the amplifier 5 is fed to the input voltage, and to the inverting inputs is the compensating voltage of the DAC.

0 4 and the correction voltage from the DAC 11 of the first conversion cycle. The accuracy of setting the compensating voltage is equal to the accuracy of sensor 7, since all the values of m most significant bits were corrected in the setup mode. Correction values are stored in memory 12 at the addresses corresponding to the high-order codes. The low-order bit weight of the D / A converter 11 must not exceed the low-order disk of the n-bit output device code being generated. The maximum correction value of the D / A converter 11 is selected on the basis of compensation for the maximum error of the D / A converter 4.

5 A Readiness signal of the A / D converter 1, delayed by the element 41, is input to the Start of the A / D converter 1. At the output of the A / D converter 1, k lower bits of the second conversion cycle are generated. The input of the adder 8 receives m

0 high bits from register 2 and k low bits from ADC 1. At the output of adder 8, an n-bit code of the converter is generated. In this case, to ensure the coupling of the codes of the first and second conversion cycles, a sign bit is entered in the second conversion cycle, as a result of which the output code of the converter code is written as n (k - 1) + m. At the end of the second cycle, the ADC 1 generates

0, the Ready signal, and at the output of element 33, a signal of the end of the transformation is produced, according to which the trigger 38 is zeroed, and the converter enters the correction mode.

Claims (2)

1. Parallel-to-serial analog-to-digital converter with automatic correction of the conversion function, which contains a memory device, an adjustable voltage source, a reversible counter, a k-discharge analog-to-digital converter, the information outputs of which are connected to the corresponding ones The bits of the first group of inputs of the adder, whose outputs are the output bus, the input of the start of the k-bit analog-to-digital converter is connected to the first output of the control unit, the first the course of which is a Start bus, the second output is connected to the control input of the first switch, the first information input of which is an input bus, and the first output is connected to the first input of the subtractive amplifier, the second input of which is connected to the output of the first digital-analog converter, which m inputs are connected with the corresponding outputs of the multiplexer, and the third input of the subtracting amplifier is connected to the output of the second digital-to-analog converter, which is characterized by the fact that, in order to increase the speed, A second switch, a code comparison unit, a register are entered, and the memory outputs are connected to the corresponding inputs of the second digital-to-analog converter and information inputs of a reversible counter, the outputs of which are connected to the corresponding information inputs of the memory, the Write-read input of which is connected to the third output of the control unit, m address inputs are combined with the corresponding m most significant bits of the second group of inputs of the adder and are connected to the corresponding the multiplexer outputs, nm low bits of the second group of inputs of the adder and nk high bits of the first group of inputs of the adder are respectively combined and are a zero potential bus, summing, subtracting and setting inputs of the reversible counter are connected respectively to the fourth, fifth and sixth outputs of the control unit, the seventh output of which is a bus. The end of the conversion; the second, third and fourth inputs of the control unit are connected respectively to the outputs Equal To, More and Less than the comparison unit of the codes, five The input is connected to the Ready output of the k-bit analog-digital converter, the eighth output is connected to the control input of the second switch and the gate input of the register, the ninth outputs are connected respectively to the first m inputs of the multiplexer and m inputs of the adjustable voltage source, the output of which connected to the second information input of the first switch, the second output of which is combined with the first output of the first switch and connected to the first the input of the second switch, the second input of which is connected to the output of the subtractive amplifier, and the first and second outputs are combined and connected to the analog input of a k-bit analog-digital converter, the k information outputs of which are connected to the corresponding first k inputs of the code comparison unit, m information outputs are connected to the corresponding information inputs of the register, the outputs of the register are connected to the corresponding second m inputs of the multiplexer, the third input of which is connected to the second output of the control unit The terminals, the second k inputs of the code comparison block, are inserted into the zero potential bus. 2. The converter according to claim 1, that is to say that the control unit is executed on six AND elements, two OR elements, a counter, a trigger, a counting trigger, and four delay elements, the input of the first element the delay is combined with the counting input of the counter and connected to the output of the first AND element, and the output of the first delay element is connected to the first input of the first OR element, the second input of which is combined with the installation input of the counting trigger, the first input of the trigger installation, second input set and trigger combined 5 with the first inputs of the second and third elements And, and connected to the output of the fourth element And, which is the seventh output of the block, the direct output of the trigger is combined with the meter installation input and 0 is the second output of the block, the inverse output is connected to the first inputs of the first AND element and the second OR element, the second input of the third AND element, the output of which is the sixth output of the block and 5 through the second delay element is connected to the first inputs of the fifth and sixth And elements and the input of the third delay element, the output of which is the third output of the block, the second inputs of the fifth and sixth And elements are the third and fourth inputs of the block, respectively, and the outputs of the fifth and sixth the first and sixth elements And are respectively the fourth and fifth outputs of the block, the clock input of the counting trigger is combined 5 with the first input of the fourth And element, the input of the fourth delay element and is the fifth input of the block, and the output is connected to the second input of the second OR element, the output of which is connected to the second input of the fourth AND element the eighth output of the block, the output of the quarter meter are the ninth outputs of the delayed delayed cell to the third input, the second input of the second element AND is the house of the first element OR, the output of which is the second input of the block, and the output is connected to is the first output of the block, the second input of the first element I. in and one Mode