RU2037267C1 - Analog-to-digital converter - Google Patents

Abstract

FIELD: pulse technique. SUBSTANCE: analog-to-digital converter has voltage-to-pulse-frequency changer, digital-to-analog converter, selector switch, electronic switch, reversing counter, control unit, AND and OR gates. Novelty is the introduction of pulse counter, two AND gates, OR gate, group of OR gates, and new design of control unit which eliminates conversion errors characteristic of prototype. EFFECT: improved conversion accuracy due to elimination of additional errors. 2 cl, 3 dwg

Description

 The invention relates to the field of pulsed technology, in particular to analog-to-digital voltage converters (ADCs) with intermediate conversion to a pulse frequency and can be used in devices for collecting analog information from control systems for technological processes and tests performed on the basis of computer technology.

 Known ADCs in which the intermediate conversion is performed using a voltage to frequency converter frequency converter [1] In the integropotentiometric ADC, errors from changing the KF conversion coefficient K are significantly reduced and increased speed is achieved.

In the ADC, higher characteristics are achieved due to the exclusion of the influence of the change in K on the conversion result and its receipt in a time equal to two periods of the generated frequencies. Therefore, this ADC is adopted as a prototype [2]
This ADC contains a voltage to pulse frequency converter, the first and second inputs of which are connected respectively to the outputs of the analog switch and key, and the output is from the first input of the control unit, the second input of which is the start bus and combined with the first input of the first OR element, the first output is connected to the control input of the key and with the first input of the second OR element, the second output with the second input of the second OR element and with the control input of the mode of subtraction of the reverse counter, and the third output with the first input of the first AND element, the second input of which is connected to the output of the second OR element, and its output with the counting input of the reverse counter, the outputs of which are the output bus of the conversion result, the input bus of the converted voltage is the information input of the analog key, the reference voltage bus is the reference input of the digital-to-analog converter, the output which is connected to the first information input of the analog switch, the second input of which is the voltage reference bus, and the control input is the bus end of the conversion and connected to the second output of the control unit, the fourth output of which is connected to the control input of the digital-to-analog converter, the information inputs of which are the output bus of the conversion result, and through a pulse shaper with the second input of the first OR element, the output of which is connected to the zeroing input of the reverse counter.

In this ADC conversion is performed in two steps. First, the VLF converts the difference between the reference U _o and input U _x voltages in a frequency f ₁ = k (U _o U _x ) and measures its period t ₁ using the frequency f _o n ₁ f _o / f ₁ f _o / k (U _o U _x ).

, в напряжение (Δ n₁), которое преобразуется ПНЧ в частоту f₂ r(Δ n₁), имеющую период t₂ 1/f₂. Этот период измеряется с помощью частоты f_o и полученный код n₂ f_o/f₂ вычитается из N_o. Полученная разность представляет собой результат преобразования Х_р.Then the code n1 is converted by a DAC having a quantum Δ

, to the voltage (Δ n ₁ ), which is converted by the IF to the frequency f ₂ r (Δ n ₁ ) having a period of t ₂ 1 / f ₂ . This period is measured using the frequency f _o and the resulting code n ₂ f _o / f ₂ is subtracted from N _o . The resulting difference is the result of the conversion of X _p .

N_o-

, т.е. Х_р соответствует входному напряжению с величиной кванта АЦП, равной Δ U_o/N_o.Indeed, substituting the values of n ₂ into X _p , and then n _1, we obtain X _p = N _o -

N _o -

, i.e. X _p corresponds to the input voltage with a quantum value of the ADC equal to Δ U _o / N _o .

This ADC has drawbacks that are caused by the fact that the measurement time U _x is t ₁ and it changes with a change in the value of U _x . This leads, firstly, to additional errors in the conversion results for Ux having a variable component whose average value exceeds the quantum Δ during the measurement time U _x . Below we will analyze the values of these errors. Secondly, additional errors will occur in the ADC from interference superimposed on U _x , because the measurement time is a multiple of or equal to the period of the interference, it can be selected only for one level U _x , and for other values of U _x interference suppression will not be executed.

 Therefore, the task is to eliminate these two types of additional errors. This proposal is aimed at solving this problem, the implementation of which will result in a positive technical effect consisting in improving the accuracy of the ADC.

 This technical effect is achieved in that in an ADC containing a voltage to pulse frequency converter, the first and second inputs of which are connected respectively to the outputs of the analog switch and key, and the output is with the first input of the control unit, the second input of which is the start bus and combined with the first input of the first OR element, the first output is connected to the control input of the key and to the first input of the second OR element, the second output is from the second input of the second OR element and with the control input of the mode of subtraction of the reverse count sensor, and the third output with the first input of the first AND element, the second input of which is connected to the output of the second OR element, and its output with the counting input of the reverse counter, the outputs of which are the output bus of the conversion result, the input bus of the converted voltage is the information input of the analog key, the bus the reference voltage is the analogue information input, the reference voltage bus is the reference input of the digital-to-analog converter, the output of which is connected to the first information input m of an analog switch, a pulse counter, second and third AND elements, a third OR element and a group of fourth OR elements, the outputs of which are connected respectively to the information inputs of the digital-analog converter, the first inputs with the corresponding outputs of the pulse counter, and the second inputs are interconnected with the inputs, are introduced resetting the pulse counter and the reverse counter to the first input of the first OR element, the output of which is connected to the control input of the digital-to-analog converter, and the second input is even the fifth output of the control unit, the first and second outputs of which are connected respectively with the first and second inputs of the third OR element, and the fifth output with the third input of the third OR element and with the first input of the second AND element, the output of which is connected to the control input of the analog switch, and the second input is the input bus of the measurement time and is combined with the first input of the third AND element, the output of which is connected to the counter input of the counter, and the second input with the third output of the control unit, the output of the third OR element is connected with the control input of the voltage to pulse frequency converter and is the bus of the conversion end, and the second information input of the analog switch is the input bus of the converted voltage.

 The control unit is made on a pulse counter, a shift register, a pulse generator, a single vibrator, a pulse shaper, the first and second elements AND, the first, second and third elements OR, the first input of the last of which is the first input of the block, the second input is connected to the output of the overflow pulse counter and combined with the first input of the first OR element, and the output with the input of the control of the shift register, the input of the first category of which is combined with the input of the same category of the pulse counter, with the synchronization input g the pulse generator is the second input of the block, the output of the first bit of the shift register is the first output of the block and is connected through the pulse shaper to the first and second inputs of the first element AND and the OR element, respectively, and the outputs of the second and third bits are the fifth and second outputs of the block, the fourth and the third outputs of the block are respectively the outputs of the first OR element and pulse generator, the last of which is connected to the second input of the first AND element and the first input of the second element and AND, the output of the first AND element is connected through a single vibrator to the third input of the first OR element, and the output of the second AND element with a counting input of a pulse counter, the discharge outputs of which are connected to the corresponding inputs of the second OR element, the output of which is connected to the second input of the second element I.

 When searching for analogues and choosing a prototype in the reviewed technical solutions, no signs were found that were similar to the distinguishing features of the claimed technical solution.

In the proposed technical solution, the problem of eliminating the disadvantages of the prototype is solved by using the input voltage U _x to form not only the frequency f ₁ but also f ₂ . In this connection time U _x equal to T _and SNN and it is given by an external signal. In addition, in the formation of f ₂ participates as a voltage proportional to the period t ₁ frequency f ₁ and voltage proportional to the time interval T _and .

The difference between t ₁ and the time of connecting to SNN latter, as will be shown below, is a value which corresponds to the mean value U _{x and} the time T and the conversion result containing no error prototype.

 In FIG. 1 shows a block diagram of a proposed ADC; in FIG. 2 and 3 is a timing diagram of his work.

 The ADC contains input buses 1 of the converted voltage and 2 reference voltages, 3 start and 4 time buses for measuring the input voltage, 5 bus of the conversion result and 6 end of the conversion, a voltage to pulse frequency converter (7), an analog switch 8, the information input of which is connected to the output when a signal is supplied to the control input, an analog switch 9, the first information input of which is connected to the output in the absence of a signal at the control input, and if it is present, the second information input is connected to the output, a digital analog converter 10 (DAC) having a memory register, information inputs for a written code and a control input for pulses to write a code into a register, a reverse counter 11 with a subtraction mode control input, a counter 12, the first 13, the second 14 and the third 15 elements And, the first 16, the second 17 and the third 18 OR elements, the fourth 19 OR elements, a control unit 20, a pulse generator 21 having a synchronization input, a counter 22, a shift register 23 having a write input "1" in the first digit and a control input for the shift pulses, single vibrator 24, pulse former 25, AND 26 and 27 elements and OR elements 28-30, bus start pulse 31 3, bus measurement 4 signal 32, pulses 33 from the output of the low-frequency converter 7, pulse 34 overflow counter 22, signals 35-37 at the outputs of the first, the second and third bits of the register 23, the signal 38 at the output of the element And 14, the pulses 39 at the output of the element OR 16, the signal 40 on the bus 6.

 In the ADC, bus 1 is connected to the information input of the key 8 and the second information input of the switch 9, bus 2 with the reference input of the DAC 10, bus 3 with the first input of the OR element 16, with the second input of the block 20 and the OR elements 19, and with the inputs of zeroing the counters 11 and 12, bus 4 with the first and second inputs of the elements And 15 and 14, respectively, bus 5 with the outputs of the counter 11, bus 6 with the control input of the frequency converter 7 and with the output of the element OR 18, the first input of which is connected to the first output of block 20, with the first input element OR 17 and the control input of the key 8, the second input with a second output 20, with the second input of the OR element 17 and with the control input of the subtraction mode of the counter 11, and the third input with the fifth output of the block 20 and with the first input of the And 14 element, the output of which is connected to the control input of the switch 9, the first information input of which is connected to the output DAC 10, and the output with the first input of the IF 7, the second input of which is connected to the output of the key 8, and the output with the first input of the unit 20, the third output of which is connected to the first and second inputs of the elements And 13 and 15, respectively, and the fourth output with the second input element OR 16, the output of which dinan with a control input of the DAC 10, the information inputs of which are connected to the outputs of the elements OR 19, the first inputs of which are connected to the corresponding outputs of the counter 12, the counting input of which is connected to the output of the element And 15, the output of the element OR 17 is connected to the second input of the element And 13, the output which is connected to the counting input of the counter 11.

 In block 20, the first input is the first input of the OR element 30, the second input is the input of the first bit of the counter 22 and is connected to the same bit of the register 23 and to the synchronization input of the generator 21, the first output is the output of the first bit of the register 23 and is connected to the first input of the element And through the former 25 26 and with the second input of the OR element 28, the second output by the output of the third category of the register 23, the third output by the output of the generator 21 and connected to the first and second inputs of the elements And 27 and 26, respectively, the fourth output by the output of the And 28 element, the fifth output by the output the second discharge of register 23, the control input of which is connected to the output of the OR element 30, the second input of which is connected to the overflow output of the counter 22 and the first input of the OR element 28, the third input of which is connected through the single-shot 24 to the output of the And 26 element, the outputs of the counter 22 are connected to the inputs of the element OR 29, the output of which is connected to the second input of the element And 27, the output of which is connected to the counting input of the counter 22.

The proposed ADC works as follows. The conversion in it is performed after the arrival of a pulse 31, which resets the counters 11 and 12, writes "1" in the first bits of the counter 22 and the shift register 23 and, passing through the OR elements 16 and 19, writes the highest code value N _m in the DAC register 10. The voltage U _m appears at the output of the latter and through the switch 9 it is supplied to the first (summing) input of the IF 7.

The signal 35 using the key 8 to the second (subtracting) input of the VLF 7 connects the input voltage U _{x of} bus 1. The same signal, passing through the OR element 18 to the control input of the VLF 7, allows its operation. If there is no signal at the control input, the VFF 7 is turned off from operation and, if it is executed, for example, on the basis of an integrator, then the integrating element is shorted.

With the advent of the signal 35, the VLF 7 starts to convert the voltage U ₁ (U _m U _x ) to the frequency f ₁ . The conversion of the period of this frequency into code n _{1 is} carried out using the counter 11 and the pulses of the generator 21 having a frequency f _o . These pulses pass through the AND element 13, which is opened by the signal 35 passing through the OR element 17, to the input of the counter 11, where the code n ₁ t ₁ f _{o is} obtained.

The same code n ₁ is generated in the counter 12, the counting input of which pulses f _o enter through the element And 15, opened by the signal 32.

 The first pulse 33 of the IFF 7 passes through the OR element 30 and shifts the "1" code from the first to the second bit of the shift register 23, forming a signal 36.

, N_o емкость регистра ЦАП 10. При этом для максимального кода N_m, соответствующего "1" во всех разрядах, т.е. N_m N_o 1, напряжение ЦАП 10 будет равно U_m Δ N_m (N_o 1) Δ U_o Δ
Для исключения записи недостоверного кода n₁, которая может произойти в момент переходных процессов в счетчике 12 при совпадении импульса формирователя 25 с импульсом f_o, в блоке 20 импульс с выхода элемента И 26 запускает одновибратор 24, а его выходной сигнал объединяется с импульсом формирователя 25 и тем самым сдвигает запись кода n₁ в регистр ЦАП 10 на время окончания переходных процессов в счетчике 12.With the end of the signal 35, the voltage U _{x is} disconnected from the subtracting input of the VFF 7, and the driver 25, with its pulse passing through the OR elements 28 and 16 (second pulse 39), writes code n ₁ from the counter 12 to the register of the DAC 10. According to this code, it voltage U _p1 Δ n _{1 is formed} , where Δ

, N _{o the} capacity of the DAC register 10. Moreover, for the maximum code N _m corresponding to "1" in all bits, i.e. N _m N _o 1, the voltage of the DAC 10 will be equal to U _m Δ N _m (N _o 1) Δ U _o Δ
To exclude the recording of an unreliable code n ₁ , which can occur at the time of transients in the counter 12 when the pulse of the shaper 25 coincides with the pulse f _o , in block 20, the pulse from the output of the element And 26 is triggered by the one-shot 24, and its output signal is combined with the pulse of the shaper 25 and thereby shifts the write code n ₁ in the register of the DAC 10 at the end of the transient in the counter 12.

The period t _{2 of the} formation of the frequency f ₂ begins with the appearance of a signal 36, which passes through the OR element 18 and supports the operation of the VLF 7, and together with the signal 32 in the And 14 element forms a signal 38. The latter, using the switch 9 to the summing input of the VLF 7, connects voltage U _x instead of U _m . During time t ₂₁ (T _and t ₁ ), the input of the VLF 7 is the voltage U _x .

Until the end of t ₂₁ , corresponding to the end of T _and , in the counter 12, the counting of the number of pulses f _o continues and its code n ₁ increases to N _and = T _and f _o , which remains in it until a new pulse 31. With the end of t _21, signal 38 is removed and the switch 9 connects to the frequency converter 7 the voltage from the output of the DAC 10, equal to U _p1 Δ n ₁ .

This voltage will be connected to the VLF 7 before the end of the time interval T _m after the start of conversion, i.e. during the time t ₂₂ T _m T _and . The time interval T _m is formed using the counter 22, counting the pulses f _o . In this case, the pulse 31 sets "1" in the low order of the counter 22 and the signal from the output of this discharge through the OR element 29 enables the operation of the And 27 element, through which the pulses from the generator 21 go to the counter input of the counter 22. The pulse 31 also synchronizes the operation of the generator 21 for elimination of time error at the initial moment in the formation of T _m . The signal at the output of the OR element 29 will be present until the code "0" appears in counter 22 in all its digits, which will happen when it is full. Given that before the formation of T _m in the counter 22, having a capacity of N _o , was written "1" code in the low order, the overflow will occur after the receipt of N _m (N _o 1) pulses fo and the duration T _m N _m / f _o ( N _o 1) / f _o .

After the end of T _m, the And element 27 is closed and a “0” code is stored in all bits of the counter 22 until a new pulse 31 appears.

The overflow pulse 34 of the counter 22, passing through the OR elements 28, 16 and 30, writes the code N _and from the counter 12 to the register of the DAC 10 (third pulse 39) and shifts the "1" code from the second to the third digit of the shift register 23, forming a signal 37 .

The output voltage of DAC 10 by changing U _n1 in its register code is changed to U Δ˙ N _{and n2.} This voltage is connected to the VLF 7 and during the time t _{23 it} participates in completing the formation of the frequency f ₂ with a period equal to t ₂ (t ₂₁ + t ₂₂ + t ₂₃ ).

 The signal 37 passes through the OR elements 17 and 18, opening the And 13 element and supporting the operation of the IFF 7, it also turns on the subtraction mode in the counter 11.

With the advent of the second pulse 33, which passes through the OR element 30 and advances the "1" code from the third bit of the shift register 23, as a result of zeroing all its bits, the signal 37 is removed and the conversion ends. For time t ₂₃ in counter 11, code n ₁ decreased by n ₂ t ₂₃ ˙ f _o and the resulting code nр is the result of the conversion n _p n ₁ n ₂ .

 Signal 40 informs about the end of the conversion and the readiness of the result np, during which the VLF 7 was allowed to work, and when it is removed, the VLF 7 is set to its initial state and a new start of the ADC into operation by pulse 31 is allowed.

When implementing the proposed ADC, it must be taken into account that, as in the prototype, a high-speed frequency converter must be used as the prototype, which allows for a change in the converted voltage during its conversion. So, for example, obtaining f ₁ and f ₂ can be carried out using the IF, which is based on the use of charge compensation of an integrating capacitor with integration of input voltages, which is implemented in the domestic integrated circuit KR1108PP.

(Т_и) преобразуемого напряжения U_x(t) за время Т_и:

(T_и)

U_x(t)dt При величине кванта АЦП Δ U_o/N_o величина n_p=

или

(I_и) Δ·n_p= Δ(n₁-n₂)
Для доказательства этого необходимо решить систему из двух уравнений, каждое из которых соответствует одному периоду частот f₁ и f₂:
f₂:

Откуда

U_x(t)dt +

U_x(t)dt U_mt₁-Δn₁(T_m-T_и)-ΔN_иt₂₃
или

+

N

Таким образом код n_р представляет собой результат преобразования, соответствующий среднему значению U_x(t) за временной интервал Т_и, который задается внешним сигналом.This ADC result obtained when measuring n _p U _x (t) _and is in during the time interval T correspond to the mean value

(T _and ) the converted voltage U _x (t) during the time T _and :

(T _and )

U _x (t) dt When the quantum of the ADC Δ U _o / N _{o the} value n _p =

or

(I _and ) Δn _p = Δ (n ₁ -n ₂ )
To prove this, it is necessary to solve a system of two equations, each of which corresponds to one period of frequencies f ₁ and f ₂ :
f ₂ :

Where from

U _x (t) dt +

U _x (t) dt U _m t ₁ -Δn ₁ (T _m -T _and ) -ΔN _and t ₂₃
or

+

N

Thus, the code n _p represents the conversion result corresponding to the average value of U _x (t) for the time interval T _and , which is set by an external signal.

(t₁)

U_x(t)dt а время t₁ изменяется с изменением величины U_x. При этом для соотношения параметров прототипа, в котором максимальная величина U_xравна U_xm= 1/2 U_o и ей соответствует получаемый результат 1/2 N_o при кванте АЦП по напряжению Δ U_o/N_o и временном кванте t_o 1/f_o 1/f_m. N_o, где f_m kU_o максимальная частота ПНЧ, время t₁ изменяется от t₁₁ 1/f_m при преобразовании U_x 0 до t₁₂ 2/f_m для U_x U_xm.In the prototype, the generated result X _p represents the average value of U _x (t) over time t ₁ , i.e.

(t ₁ )

U _x (t) dt and the time t ₁ varies with the value of U _x . Moreover, for the ratio of the parameters of the prototype, in which the maximum value of U _x is U _xm = 1/2 U _o and the result obtained is 1/2 N _o for the ADC quantum in terms of voltage Δ U _o / N _o and the time quantum t _o 1 / f _o 1 / f _m . N _o , where f _m kU _{o is the} maximum VLF frequency, the time t ₁ varies from t ₁₁ 1 / f _m when converting U _x 0 to t ₁₂ 2 / f _m for U _x U _xm .

(t₁₂). Тогда для других значений U_x величина последней будет изменяться и это приводит к дополнительным погрешностям в Х_р от

(t₁), величины которых различны для различных уровней U_x при одинаковой величине U_п(t).Such a change in the measurement time t ₁ of U _x (t) leads to the fact that in the presence of the last variable component U _p (t), the obtained result X _p should be used taking into account t ₁ . But this was not fulfilled in the prototype, and therefore it is advisable to accept that the results of X _p correspond to the average values of U _x (t) and U _p (t) during the time t ₁₂ 2 / t _{m of} the voltage conversion U _x = U _xm , for which the average value of the variable component is equal

(t ₁₂ ). Then for other values of U _{x the} value of the latter will change and this leads to additional errors in X _p from

(t ₁ ), the values of which are different for different levels of U _x at the same value of U _p (t).

U

f_m, т.е. входное напряжение U_x(t) U_x + U_п(t) U_x + V_t˙t, величина

(t₁)

V_tt₁=

U

f_m·t₁ и она принимает значения от 1/4 qU_xm для t₁₁ при U_x 0, до 1/2 qU_xmдля t₁₂ при U_x U_xm. Дополнительная погрешность для этого вида U_п(t) может достигать величины 1/4 qU_xm, например, при q 10% ее величина относительно наибольшего преобразуемого напряжения U_xm будет составлять 2,5%
Если U_п(t) имеет синусоидальную форму, например, она является наложенной на U_x(t) помехой от переменного напряжения сети питания, т.е. входное напряжение U_x(t) U_x+U_пsin(ωt+φ_o),
где ω 2 π f_m,
f_n частота помехи;
φ_о фазовый сдвиг относительно начала времени измерения, то средняя величина

(t₁)

U_пsin(ωt+φ_o)dt

·sin(πt₁f_п)·sin(πt₁f_п+φ_o) При t₁ р/f_п она будет равна

(t₁)

· sin(πp)·sin(πp+φ_o) а при выборе t₁₂
1/f_п или f_m 2f_п будет выполняться подавление U_ппри преобразовании U_x U_xm. Но при этом для U_x 0 при t₂₁

, когда p 1/2 и при φ_о 0 будет наибольшая величина погрешности от

(t₁₁)

0,64 U_п. Например, для U_п 5% U_xm величина этой погрешности относительно наибольшего преобразуемого напряжения U_xm будет составлять 3,2%
В предлагаемом АЦП при сохранении величин квантов по напряжению и во время 1/f_o прототипа и при выборе времени измерения Т_и t₁₂ N_m/f_oдополнительные погрешности в 2,5% и 3,2% для приведенных примеров величин U_п(t) в результате преобразования будут исключены, так как для всех уровней U_x(t) время его интегрирования остается равным Т_и. Необходимо отметить, что величина времени измерения в этом АЦП может изменяться и задаваться по внешнему сигналу. Если она изменяется от Т_идо (Т_и+Т_д)=(N_m+N_д)

, то при реализации АЦП и сохранении величин Δ и f_o необходимо увеличить опорное напряжение U_o на Δ N_д, а также емкость счетчиков 12 и 22 на N_д, обеспечив ее, равной N_o + N_д.So in the presence of U _p (t) changing during t ₁ according to the linear law with a speed V _t = g

U

f _m i.e. input voltage U _x (t) U _x + U _p (t) U _x + V _t ˙t, value

(t ₁ )

V _t t ₁ =

U

f _m · t ₁ and it takes values from 1/4 qU _xm for t ₁₁ at U _x 0, to 1/2 qU _xm for t ₁₂ at U _x U _xm . An additional error for this type of U _p (t) can reach 1/4 qU _xm , for example, at q 10%, its value relative to the largest converted voltage U _xm will be 2.5%
If U _p (t) has a sinusoidal shape, for example, it is superimposed on U _x (t) interference from an alternating voltage of the power supply, i.e. input voltage U _x (t) U _x + U _п sin (ωt + φ _o ),
where ω 2 π f _m ,
f _n interference frequency;
φ _{about the} phase shift relative to the beginning of the measurement time, then the average value

(t ₁ )

U _p sin (ωt + φ _o ) dt

Sin (πt ₁ f _p ) sin (πt ₁ f _p + φ _o ) At t ₁ p / f _p it will be equal to

(t ₁ )

Sin (πp) sin (πp + φ _o ) and when t ₁₂
1 / f _p or f _m 2f _n suppression will be performed when converting _n U _x U U _xm. But at the same time for U _x 0 at t ₂₁

when p 1/2 and when φ _о 0 there will be the largest error from

(t ₁₁ )

0.64 U _p . For example, for U _p 5% U _{xm, the} value of this error relative to the largest converted voltage U _xm will be 3.2%
In the proposed ADC, while maintaining the values of the quanta of voltage and during 1 / f _{o the} prototype and when choosing the measurement time T _and t ₁₂ N _m / f _o additional errors of 2.5% and 3.2% for the above examples of values of U _p ( t) as a result of the transformation, they will be excluded, since for all levels U _x (t) the time of its integration remains equal to T _and . It should be noted that the value of the measurement time in this ADC can be changed and set by an external signal. If it is changed from T _and w (T _u + T _g) = (N _m + N _d)

, then when implementing the ADC and maintaining the values of Δ and f _o it is necessary to increase the reference voltage U _o by Δ N _d , as well as the capacity of the counters 12 and 22 by N _d , providing it equal to N _o + N _d .

 All this shows that the inventive ADC has advantages over the prototype when using it, and the implementation of the ADC does not cause any difficulties, since nodes such as the prototype can be used to build it.

 Thus, due to the elimination of additional errors arising in the prototype, the claimed ADC solves the problem posed to it, eliminates the disadvantages of the prototype and achieves a technical effect to improve the accuracy of its operation.

Claims (2)

 1. ANALOG-DIGITAL CONVERTER, comprising a voltage to pulse frequency converter, the first and second inputs of which are connected respectively to the outputs of the analog switch and key, and the output with the first input of the control unit, the second input of which is the start bus and combined with the first input of the first element OR , the first output is connected to the control input of the key and to the first input of the second OR element, the second output with the second input of the second OR element and the input of the control mode of the subtraction of the reversible counter, and the third the output with the first input of the first AND element, the second input of which is connected to the output of the second OR element, and its output with the counting input of the reverse counter, the outputs of which are the output bus of the conversion result, the input bus of the converted voltage is the information input of the analog switch, the reference voltage bus is the reference input digital-to-analog converter, the output of which is connected to the first information input of the analog switch, characterized in that a pulse counter is introduced into it, the second and third AND elements, a third OR element, and a group of fourth OR elements, the outputs of which are connected respectively to the information inputs of the digital-to-analog converter, the first inputs with the corresponding outputs of the pulse counter, and the second inputs are combined with each other and with the inputs of zeroing the pulse counter and the reverse counter and with the first input of the first OR element, the output of which is connected to the control input of the digital-to-analog converter, and the second input with the fourth output of the control unit, the first and second outputs of which are connected respectively, with the first and second inputs of the third OR element, and the fifth output with the third input of the third OR element and the first input of the second AND element, the output of which is connected to the control input of the analog switch, and the second input is the input bus of the measurement time and combined with the first input of the third AND element, the output of which is connected to the counter input of the counter, and the second input to the third output of the control unit, the output of the third OR element is connected to the control input of the voltage to pulse frequency converter and is the conversion end bus, and the second information input of the analog switch is the input bus of the converted voltage.  2. The Converter according to claim 1, characterized in that the control unit is made on a pulse counter, a shift register, a pulse generator, a single vibrator, a pulse shaper, the first and second AND elements, the first, second and third OR elements, the first input of the last of which is the first input of the block, the second input is connected to the overflow output of the pulse counter and combined with the first input of the first OR element, and the output with the shift register control input, the first bit of which is combined with the input of the same name bit and the pulse counter, with the synchronization input of the pulse generator and is the second input of the block, the output of the first bit of the shift register is the first output of the block and through the pulse shaper is connected to the first and second inputs of the first AND element and the OR element, respectively, and the outputs of the second and third bits are respectively the fifth and second outputs of the block, the fourth and third outputs of the block are respectively the outputs of the first OR element and pulse generator, the last of which is connected to the second input ne of the first AND element and the first input of the second And element, the output of the first And element is connected through a single vibrator to the third input of the first OR element, and the output of the second And element with the counting input of the pulse counter, the discharge outputs of which are connected to the corresponding inputs of the second OR element, the output of which is connected to the second input of the second element I.