SU1200421A1 - Analog-to-digital converter - Google Patents

Abstract

. ANALOG-DIGITAL CONVERTER containing a storage capacitor, the first plate of which is connected to the common bus, the first inputs of the first and second comparators are combined, connected to the second plate of the storage capacitor and the outputs of the first and second controlled current sources, the control inputs of which are connected respectively to the first and the second outputs of the control and recording unit; the first input of the analog switch is connected to the third output of the control and recording unit; the outputs of the first and second comparator They are connected respectively to the first and BTopt iM inputs of the control and recording unit, characterized in that, in order to improve accuracy, a resistor, a comparison unit, a correction unit, a third controlled current source, the output of which is connected to the second input of the second comparator, are inserted into it The first terminal of the second comparator and the first terminal of the resistor, the second terminal of which is combined with the second input of the first comparator and is the input bus, the first input of the first comparator is combined with the first input of the correction unit, the second input cat The third input is combined with the first input of the third controlled current source and is a power bus, the second input of the third controlled current source is connected to the output of the correction unit, and the second capacitor capacitor plate is connected to the second INPUT analog key, the output of which is connected to the common bus, the fourth output of the control and recording unit is the bus of the least significant bits, the fifth output is the high order of the higher bits and is connected to this first input of the middle Neny, the second input of which is a bus setpoint code, and an output coupled to a third input of the control unit and recording a fourth input is a bus start as well. the sixth output is connected to the fourth input of the correction unit, the second output is connected to the third input of the second comparator. 2. The converter according to claim 1, characterized in that the control and recording unit is convoluted on four triggers, two one-oscillators, three counters, a clock pulse generator, five elements

Description

And, the first input of the first trigger is the fourth input of the control and registration unit, the second input of the first trigger is connected to the output of the first one-oscillator, the inverse output of the first trigger is the third output of the control and recording unit, the input of the second single-oscillator is combined with the first inputs of the second one and the third trigger and connected to the direct output of the first trigger, the second input of the second trigger is combined with the second input of the third trigger, with the first inputs of the first, second and third elements And is connected to you the clock pulse generator, wherein the first inputs of the first, second, third counters and the third input of the second trigger are combined and connected to the output of the second one-oscillator; the fourth input of the second trigger is the first input of the control and recording unit; the inverse output of the second trigger registration and connected to the second input of the second element And the first input of the fourth element And is combined with the first input of the fourth trigger and is connected to the direct output of the second trigger, the second The fourth trigger is connected to the common bus, the third input is connected to the output of the first counter, the second input of which is connected to the output of the first element I, the second input of which is combined with the first input of the fifth element And and connected to the inverse output of the fourth trigger, the direct output of which is connected to the second input of the fourth element AND, the output of which is connected to the third input of the third trigger, the direct output of which is the second output

control unit and registration and is connected to the second input of the third element I, the third input of which is combined with the input of the first one-shot and is the second input of the control and recording unit, and the output is connected to the second input of the third counter whose output is the fourth output of the control and registration unit whose fifth output is connected to the output of the second counter,. the second input of which is connected to the output of the second element I, the third input of which is the second input of the control and recording unit, the third input of the block of which is the second input of the fifth element I, the output of which is the sixth output of the control and registration unit.

3, The converter according to claim 1, similar to the fact that the correction unit is made on a reversible counter, a digital-to-analog converter, two resistors, a comparator transistor, the first input of which is the first input of the correction unit, the second input is combined with the first terminals of the first resistor and connected to the collector of the transistor, and the output to the first input of the reversible counter, the second input of which is the fourth input of the correction unit, and the output connected to the input of a digital-analogue converter, the output of which is connected to the base of the transistor This is the output of the correction unit, when the emitter emitter of the transistor is connected to the first output of the second resistor, the second output of which is the third input of the correction unit, the second output of the first resistor is the second input of the correction unit.

The invention relates to a measurement technique and is intended to convert an input voltage into a code.

The aim of the invention is to improve the accuracy of the analog-digital conversion.

Figure 1 presents the functional diagram of the analog-to-digital Converter; in fig. 2-4 - graphics, as shown in his work; in fig. 5 is a schematic diagram of the control and registration unit; FIG. 6 shows timing charts explaining his work; FIG.

But FIG. 7 is a schematic diagram of a correction unit.

The A / D converter contains input bus 1, controlled current sources 2-4, resistor 5, first 6 and second comparators 7, correction unit 8, control and recording unit 9, comparison unit 10, setpoint code bus 11, output code bus 12 high-order bits, low-bit output code bus 13, storage capacitor J4, analog switch 15, power supply bus 16, reference voltage source bus 17, Start signal bus 18.

The control and registration unit 9 contains a trigger 19, a one-shot 20, a trigger 21, an element 22, a trigger 23 and 24, an element 25, a counter 26, an element 27, an oscillator 28 clock pulses, an element 29, a counter 30, an element 31 , counter 32, one-shot 33, Correction block 8 with a digital integrator Fig. 7} contains a comparator 34, a reversible counter 35, a digital-to-analog converter 36, resistors 37 and 38, and a transistor 39.

The device works as follows.

In the initial state, the capacitor 14 is discharged to zero using a closed switch 15. Sources 2 and 3 of the current are disconnected from the capacitor 14. Input voltage bus 1 supplies the converted voltage U, (,, while the outputs of the Comparators 6. and 7 .- logical zero.

. In the control and registration block 9 of FIG. 5) in the initial state, the trigger .21 is in the single state, the trigger 23 is in the zero state. The Trigger signal is triggered by the Start signal: 19 and the key 15 is opened, the one-shot 20 is simultaneously started, the front of which counters 26, 30 and 32 are turned on. After the end of the pulse of the single vibrator, the trigger 21 is set to the zero state after the first pulse from the generator 28. The delay on the one-shot 20 is necessary to reliably unlock the key 15, since its turn-off time may be longer than the turn-on time of the controlled current source 2, which is activated by trigger 21. From the moment the current source 2 is turned on, the voltage

on the capacitor 14 it starts to increase linearly in time (Fig. 2), and during the period of the pulse repetition period of the generator 28, the voltage on the capacitor changes to, h, where h is a quantum. ADC and an integer proportional to the base of the digital equivalent system (for the Binary system.

a is proportional to degree 2. For the highest speed, the number d must be equal to

(I)

max)

where is the number of quanta

ADC.

Simultaneously with the charge of the capacitor 14, the pulses from the generator 28 through the element 29 are counted by the counter 30.

When the voltage across the capacitor 14 p1) is equal to Uj (, then the output of the first comparator is logical 1, however, the capacitor 14 continues

charged. By a pulse from the generator 28, the trigger 21 is set to one and the controlled current source 2 is disconnected from the capacitor 14, and the pulses from the generator 28

stop entering counter 30. In counter 30, a number equal to

m

(2)

where is the nearest smaller integer

number.

The number M determines the value of the highest digit of the digital equivalent.

40.U} (.. Simultaneously, the trigger 24 is set to the zero state and the pulses from the generator 28 through the element And 25 begin to flow into the counter 26. During operation of the counter 26

45, the voltage across the capacitor 14 does not change (Fig. 2). The volume of the counter 26 is equal to the number m, therefore, through m pulses. The trigger 24 is set to one state and the counter 26

50 stops its work. The next pulse of the generator 28, the trigger 23 is set to one state, since the logical 1 is fed to its D input via the AND 22 element,

55 and with this. A controlled current source 3 is switched on, the value of which is 3 2, / a,. The voltage on the capacitor 14 during charging from J current source 3 varies by the value of h in time T. Simultaneously with switching on current source 3, trigger 23 is fed to the second comparator 7 and logical 1 appears at its output. Pulses from the generator 28 through the element And 31 are counted by the counter 32, Since the second input of the second comparator 7 is set to a voltage equal to and, + l, -k, the value of the current of the controlled current source 4, and -, when u is converted to the second voltage the comparator is set to zero state rf n The counting of the pulses by the counter 32 is stopped. In the counter, the value of the lower bits of the digital equivalent will be recorded. Indeed, the change in voltage on the capacitor 14 is equal to and -1- H - (M + i) H U; j - MN. The number recorded in the counter 32 is equal to Ex.J «i corresponds to the value of the lower bits of the digital equivalent. After the pulse decay from the second comparator 7, the one-shot 33 is triggered, the pulse from which sets the trigger 19 to the initial state, after which the key 15 is closed, the capacitor 14 is discharged, the triggers 21 and 23 are reset, the controlled sources 2 and 3 the current is disconnected from the capacitor 14. The device returns to its original state, and the conversion result is stored in the counters 30 and 3. For the worst case, the maximum conversion time does not exceed 2 (a, -1) -TQ. Due to the on and off delay of the first controlled current source 2, the voltage on the capacitor 14 at the moment the current source 2 is turned off will not be equal to an integer number of quanta H, which leads to a large error in the converter. Indeed, for example, the charge of the capacitor 14 is carried out in a time longer than an integer T by a value of r. This is equivalent to 1 voltage increase of the voltage by an & H 3, / C, and the conversion error is 1 8 4 To eliminate this error, the comparison voltage at the second input of the second comparator 7 is set to a DN greater than that defined by expression 3 (Fig. 2, then at the second conversion stage, no error occurs. However, when the temperature changes, either from aging of the elements or due to inaccurate adjustment, the equivalent value of t changes, which entails additional errors. To eliminate these additional errors in the ADC, correction unit 8 is used, which changes the values current 3 controlled source 4 current so that when the voltage on the capacitor 14 is changed by uU after the current source 2 is terminated due to the change in r, the threshold voltage of the second comparator 7 changes by the same value Jj, Correction This is carried out simultaneously with the signal conversion, but not for each sample of the input signal, but only for samples whose higher-order codes are the same as the setpoint code. If the distribution of signals is uniform, then the value of the setpoint code is arbitrary. The correction frequency is / a ,,. (6) is the frequency of signal samples. de fe ,, 6 If the distribution of the input signal is not uniform, then the setpoint code should be selected close to the median value of the distribution of the signal. In this case, the correction frequency will be greater than that determined from expression 6. Consider the case of error correction when the signal U is input) (the higher bits of the digital equivalent of which coincide with the bus setpoint code 1 .. The correction unit works with a digital integrator (FIG .7) as follows. As in the previous case, during the correction, the comparator FOR compares two voltages (M + 1) H + + DN, and EO „+ D, R (M-I) N + lN. For example, if, then this means that it is necessary to increase the current v) j, i.e. in a reversible counter, one pulse is taken away, formed by element 28 (output 1 of control and recording unit 9) (FIG. 6), the voltage at the output of the DAC 36 decreases, and the current through transistor 39 increases, causing an increase in current 0 as in a transistor 39, and in the transistor of the third current source 4 218, thereby the difference between iH and dN is reduced. In the second correction, this difference will be further reduced, etc. As for the correction block with analog integration, in one correction step the value of approaching H to LF should not exceed 0.25 h, so that there is no strong yawing of the correction voltage .

(/,

Fy

II 11

Claims (3)

1. ANALOG-DIGITAL CONVERTER containing a storage capacitor, the first lining of which is connected to a common bus, the first inputs of the first and second comparators are combined, connected to the second lining of the storage capacitor and the outputs of the first and second controlled current sources, the control inputs of which are connected respectively to the first and the second outputs of the control and registration unit, the first input of the analog key is connected to the third output of the control and registration unit, the outputs of the first and second comparators respectively, with the first and second inputs of the control and registration unit, characterized in that, in order to increase accuracy, a resistor, a comparison unit, a correction unit, a third controlled current source, the output of which is connected to the second input of the second comparator, are introduced the output of the second comparator and the first output of the resistor, the second output of which is combined with the second input of the first comparator and is the input bus, the first input of the first comparator is combined with the first input of the correction unit, the second input of which is is a reference voltage bus, the third input is combined with the first input of the third controlled current source and is the power bus, the second input of the third controlled current source is connected to the output of the correction unit, while the second lining of the storage capacitor is connected to the second input! an analog key, the output of which is connected to a common bus, the fourth input of the control and registration unit being the low-order bus, the fifth output being the high-order bus and connected to the first input of the comparison unit, the second input of which is the setpoint code bus, and the output is connected to the third the input of the control and registration unit, the fourth input is the Start bus, and. the sixth output is connected to the fourth input of the correction unit, the second output is connected to the third input of the second comparator. 2. The Converter according to claim 1, characterized in that the control and registration unit is made up of four triggers, two one-shots, three counters, a clock, five elements SU „„ 1200421 And, at the same time, the first input of the first trigger ¹ is the fourth input of the control and registration unit, the second input of the first trigger is connected to the output of the first one-shot, the inverse output of the first trigger is the third output of the control and registration, the input of the second one-shot is combined with the first inputs of the second and third trigger and connected to the direct output of the first trigger, the second input of the second trigger is combined with the second input of the third trigger, with the first inputs of the first, second and third elements And and connected to the output a clock generator house, the first inputs of the first, second, third counters and the third input of the second trigger combined and connected to the output of the second one-shot, the fourth input of the second trigger is the first input of the control and registration unit, the inverse output of the second trigger is the first output of the control and registration unit and connected to the second input of the second element And, the first input of the fourth element And is combined with the first input of the fourth trigger and connected to the direct output of the second trigger, the second input the fourth trigger is connected to a common bus, the third input is connected to the output of the first counter, the second input of which is connected to the output of the first element And, the second input of which is combined with the first input of the fifth element And connected to the inverse output of the fourth trigger, the direct output of which is connected to the second input the fourth element And, the output of which is connected to the third input of the third trigger, the direct output of which is the second output of the control and registration unit and connected to the second input of the third element And, the third input of which inen with the input of the first one-shot and is the second input of the control and registration unit, and the output is connected to the second input of the third counter, the output of which is the fourth output of the control and registration unit, the fifth output of which is connected to the output of the second counter, the second input of which is connected to the output of the second element And, the third input of which is the second input of the control and registration unit, the third input of which is the second input of the fifth element And, the output of which is the sixth output of the control unit and p registration. 3, The converter according to claim 1, characterized in that the correction unit is made on a reversible counter, digital-to-analog converter, two resistors, a transistor, a comparator, the first input of which is the first input of the correction unit, the second input is combined with the first output of the first resistor and connected to the collector of the transistor, and the output to the first input of the reverse counter, the second input of which is the fourth input of the correction unit, and the output is connected to the input of the digital-to-analog converter, the output of which is connected to the base of the trans Operations and is the output correction unit, wherein the emitter of the transistor connected to the first terminal of the second resistor, a second terminal which is a third input of the correction unit, the second terminal of the first resistor is a second input of the correction unit.