SU1481803A1 - Logarithmic analog-digital converter - Google Patents

Abstract

The invention relates to the conversion of information from analog to digital form and can be used in measuring, converting and computing equipment, as well as in automatic control systems. The purpose of the invention is to improve the accuracy of the conversion. The logarithmic analog-to-digital converter (ADC) contains a reference voltage source, two switches, an exponential voltage generator (LEG) with an input for adjusting the constant time of the exponents, analog and digital comparators, two D - triggers, And element, one-shot, two counters, register, synchronization unit, reference pulse generator, digital-to-analog converter (D / A converter) and integrator. The logarithmic ADC works on the basis of a comparison of the exponential voltage of the HEG with two reference and measured voltages and forming parallel measuring and calibration intervals using D - triggers, which are converted into digital code by the first and second counters. The code of the calibration interval is compared with the digital constant and, based on the results of the comparison, the voltage of the constant-time exponent of the LEGs is generated by using the DAC and the integrator. 2 Il.

Description

The invention relates to devices for converting analog information into digital form and can be used in automation, measurement, conversion, and computer technology, as well as in control systems.

The purpose of the invention is to improve accuracy.

FIG. 1 shows a functional diagram of a logarithmic analog-to-digital converter; figure 2 is a timing diagram of his work.

The logarithmic analog-to-digital converter (LATsP) contains the source 1 of the reference voltage, the first switch 2, the exponential voltage generator 3 (LEG) with an adjustable time constant of the exponent, the first 4 and the second 5 counters, the analog comparator 6, element I 7, the one-shot 8, two D-flip-flops 9 and 10, (synchronization unit 11, register 12, digital comparator 13, two-digit digital-to-analog converter (D / A converter) 14, integrator 15, generator

oo

,

00 00

314

16 support pulses, a second switch 17, an analog input 18, a digital input 19 sets the initial code of the exponent of the constant-time control circuit and a digital output 20 ycTpouctsa.

LA1SH works as follows.

The analog input 18 of the device receives the measured voltage Ux, and the digital input 19 receives a constant Nxo code. The start-up pulse 29 from the synchronization unit 11 generates the exponential voltage generator 3 to its maximum voltage U5.

At the end of this pulse, exponential voltage 31 begins to form T. Pulse 30 resets counters 4 and 5 and presets D-triggers: trigger 9 is set to O, and trigger 10 is set to 1 if they were in other states x (srach after power on).

Due to the zero code on the control inputs of the first 2 and second

The switch 17 switches on their first channels, so that the output of the first switch 2 receives the first reference voltage U01 from its first input (Fig. 2, diagram 32). This voltage and the exponential decay voltage from the HENG 3 are fed to the inputs of the comparator 6 and are compared in it. For now, U0 is more than the leg 3 voltage.

At the output of the analog comparator 6, O is present (diagram 33). In this state, the information input on the trigger 9 has a log. 1 from the output of the second switch 17, and at the information input of the trigger 10 there is a Log. About from the output of the high bit of the calibration counter 4 (diagram 34).

At the moment of the TZ, the exponential voltage becomes less than the reference U0 (and, at the output of the analog comparator 6, a positive differential is generated, which, entering through the And 7 element at the clock inputs of the flip-flops 9 and 10, causes them to tilt according to the signals at their information inputs. It should be noted that at the second input of the element And 7 all this time is Log.1 (Fig. 2, diagram 38), since one of the new vibrators 8 has an inverse output. Thus, at the direct output, the first 1803

 four

of the first trigger 9, the leading edge of the measuring time interval Ti 37 is formed, and at the inverse output of the second trigger 10 - the calibration interval T 35. Both counters 4 and 5, according to the counting resolution signals, start the frequency pulses from the generator 9 and 10

sixteen.

Signal Log. 1, the inverted output of the trigger 10 acts on the low-order control inputs of the switches 2 and 17 and switches them to the second channels, with the result that the second input of the analog comparator 6 receives the measured voltage U,, & to the information input of the D-flip-flop 9 - signal Log. A. Because and,:

U ,,, then at time T the analog comparator 6 returns to O.

At time T, the exponential voltage 31 becomes less than the measured one and the comparator 6 produces a second positive differential that causes the trigger 9 to return to its original zero state in accordance with the signal at its information input. The formation of the measurement interval ends. The duration of the measuring interval Tm is equal to: Ti T5 - T3

, 1 u ot / v

 c, -In -, where c-- is constant

the exponential voltage of the LEG 3. The output code of the counter 5 is equal to

N - f, G In --21- n hl, ° e1P them

(ABOUT

The second trigger 10 at time T5 remains in state O since LoG acts at its information input. Oh, starting from the moment Tr, until the moment T6. In the moment

a time T6 at the output of the most significant bit of the counter 4, a log appears. 1. This leads to switching switches 2 and 17 to third channels and connecting to the second input of the comparator

6 second reference voltage U0Ј

(U0 ,, U0,). The comparator output signal is set to O. Thus, the LACP circuit is prepared for fixing the end of the calibration

interval.

The considered time interval T6-Tz, in which the voltage of the inheritor 3 varies, determines the measurement range

DM input voltage, which is related to the size of the n counters 4 and 5 and the resolution of the LATCP as follows

Bee 2 ™ -.

At time T7, the exponential voltage of the LEG 3 becomes less than the second reference voltage Uoi, while a positive differential is generated at the comparator 6, which causes the second trigger 10 to tilt (as the signal at its information input changed at time T6). The formation of the calibration interval Tk ends

Tk T7 - T

/ -1 UCM

e1p

 04

code 4 is set on counter 4

 f

on

Uh oh

In -,

ot

(2)

which is compared on digital comparator 13 with a constant initial code N ko.

From the moment T-, to T8, the output of the More-and less digital comparator 13 of the result of the comparison of the codes occurs. At the time Tg, the pulse 28 from the output of the synchronization unit 11 records information in the register 12 and the two-bit DAC 14. The register 12 records the NM code of the measured voltage, i.e. The conversion result is updated. In a two-bit DAC t4, the result of the code comparison is stored, which is stored therein during one conversion period.

Analog two-pole voltage from the output of the DAC 14, which has the following relay characteristic -E, if NK Nko; Oh, if Nk NKO; - + Е „, if NK NKO,

enters the integrator 15 and more from the output of the integrator 15 to the input of the control of the time constant of the exponential voltage of the LEG 3.

The time constant of the integrator 15, taking into account the value of E p, is chosen such that during the time of the falling portion of the exponential voltage, the change in the output voltage of the integrator 15 does not exceed the equivalent of 0.5 code unit of code N.

Thus, using the considered adjustment circuit, the counter code

NK NKO

(3)

with an error not exceeding the unit of account, since the comparison is carried out in digital form by a digital comparator 13. From (1) - (3) there is

20 lg ЯN NKO

U)

20 lg HЈL

(four)

U

02

whence it is seen that the output LACP code is proportional to the logarithm of the ratio of the measured and reference voltages.

With an increase (during transients when power is turned on), the calibration interval is bounded above by the value (T.-T) of the pulse 30 of the preset trigger 9 and 10. If the reduction in e is too low below the minimum allowable value

(this case is marked on the diagram 31 by a dotted line) the third positive difference at the output of the comparator 6 is absent (the dashed line at diagram 33), therefore, the calibration interval Tk is limited from the bottom by a negative pulse 38 from the output of the one-shot 8 through the element 7 to eliminate the sign inversion connection through the adjustment circuit Јe.

An operational test of the performance of the LACP is performed by removing the input voltage.

As can be seen from time diagrams 31 and 32, there is no positive difference at time T, and the output voltage of comparator 6 (diagram 33) is zero up to time T7, i.e. the first trigger 9 is triggered simultaneously with

the second 10 at time T7 and the measurement interval becomes equal to the calibration Ti Ti. In this case, the output code of the LATCP NM NKo, which is the performance criterion

total latsp.

When choosing LACP parameters, one should take into account that the value of the code Nj, 0 is determined by the range of reference voltages

D, 20 lg g "- (5)

and 01 and the required resolution

- Dk

 T

and the exponential time constant is related to the reference frequency by the relation (2), which, taking into account (5) and (6), gives C Mge

 Lf, -.

The value determines the speed of the converter.

Practically with a reference frequency of several megahertz and the required resolution, for example, & 0.01 dB are achievable in a fraction of a millisecond and an error not exceeding a fraction of a decibel.

Thus, in LACP, by introducing an automatic constant-time adjustment circuit for exponents of the LEG 3, the conversion accuracy is improved by reducing the slowly varying error components due to the departure of LEG 3 parameters and other LACP elements.

Claims (1)

Invention Formula A log-analog-to-digital converter containing a source of reference voltages, an integrator, an analog comparator, a one-shot, first and second, triggers, an element, first and second counters, and a reference pulse generator, characterized in that transformations, in it the first and second triggers are made in the form of D-triggers and the first and second switches, an exponential voltage generator, a digital comparator, a register, a digital-to-analog converter and a synchronization unit, whose input is about A reference pulse generator is connected with the counting inputs of the first and second counters and the first output of the synchronization unit is connected to the installation inputs of the first D-flip-flop, the first and second counters, and the installation input of the second D-flip-flop, The second output of the synchronization unit is connected to the start input of the exponential voltage generator, the output of which is connected to the first input of the analog comparator, the second input of which is connected to the output of the first switch, the first information input of which is connected with the first output of the reference voltage source, the second and third information inputs of the first switch are connected respectively to the analog input of a logarithmic analog-digital converter and the second output of the reference voltage source, the output of the analog comparator is connected to the first input of the And element, the second input of which is connected to the inverse output one-shot, the output element And is connected to the clock inputs of the first and second D-flip-flops, the information input of the first D-flip-flop is connected to the output of the second switch The first information input of which is connected to the logical 1 bus, the second and third information inputs of the second switch are connected to the logical O bus, the direct output of the first D-flip-flop is connected to the counting enable input of the first counter, the bits of which are connected to the information inputs of the register, the outputs the bits of which are the digital output of the device, the inverse output of the second D-flip-flop is connected simultaneously with the first control inputs of the first and second switches and the input of the resolution of the second account The bit, the bit output of which is connected to the first input of a digital comparator, the second input of which is connected to the input of the calibration interval of a logarithmic analog-digital converter, the output of the digital comparator is connected to the information input of a digital-analog converter, the synchronization input of which is combined with the register recording input and connected to the third output of the synchronization unit, the output of the digital-to-analog converter is connected to the information input of the integrator, the output of which is connected to the input controlling the generator time constant of the exponential voltage, the high-voltage output of the second counter is connected to the information input of the second D-flip-flop, to the second control inputs of the first and second switches, and to the single-shot start input. J buff. ,  G "Ya7 G / / F 0s; J-i- P-