SU924624A1 - Digital pulse signal recorder with automatic range switching - Google Patents

Description

The invention relates to electrical measuring technology and can be used in the development of a device for measuring and recording pulse shape. The closest in technical essence to the present invention is a digital pulse recorder with automatic range switching, consisting of a series-connected automatic range switch and a digital pulse recorder, a scaling unit, the input of which is connected to the bus of the signal under study and the input of the trigger unit, the output of the connected to the input of the delay unit, the first output of the associated .with the second input of the storage unit, the first input of which is connected to the output analogue -Digital converter, an input connected to the output of the switch tl. A disadvantage of the known device is that it does not provide an optimal selection of the measurement range for the entire implementation of the input signal with a minimum amount of redundant information about the states of the ranges - when registering alternating pulse signals of complex shape, switching can be continuous during the entire recording, which leads to large amount of additional information about the selected ranges. The purpose of the invention is to provide an optimal selection of the measurement range for the entire implementation of the input signal with a minimum amount of redundant information on the range states. The goal is achieved by the fact that a digital recorder of pulse signals with automatic switching of ranges, containing a scaling unit, the input of which is connected to the bus of the signal under study and the input of the triggering unit, the output of the subclamp to the input of the delay unit, the first output connected to the second input of the storage unit, the first the input of which is connected to the output of the analog-digital converter, the input of the switch connected to the output, is provided with analog-discrete delay lines, a block of clock generators frequency, block overloading block and decoder, whose inputs are connected to the outputs of the band overload fixing block, the output to the third input of the memory block and the control input of the switch, and the control input to the second output of the delay block and the control input of the generator block the clock frequency, the output of which is connected to the clock inputs of the analog-discrete delay lines, the conductors of which are connected to the switch inputs, and the inputs to the output, the scaling block ladders and the inputs of the overload fixing unit , New.

The drawing shows a structural electrical circuit of the device.

The device consists of scaling unit 1, analog-discrete lines 2, delay, switch 5, analog-digital converter 6, storage unit 7t & There are 8 generators of clock frequency, block 9 of fixation of band overload, decoder 10, block 11 of start and block 12 of delay. 8 in general, the number of the range-E5 of the scaling unit 1 and the corresponding delay lines can be arbitrary. The drawing shows a variant of the device with three ranges and the scaling unit 1 has three outputs where the signal level differs by a number proportional to the range. The highest signal level occurs at the first output of block 1, to which the analog-discrete line 2 of delay c is connected.

Analog-to-discrete delay lines are elements of analog information storage that are controlled by clocking.

The instantaneous value of the input signal, introduced into the delay line, is clocked through all the elements of the delay line and outputted by delaying the input signal over time. Depending on the period of the clock pulses, a different delay in time on the same delay line can be made. The period of the clock pulses generated by the generator unit 8 depends on the appearance of the signal at the second output of the delay unit 12. The trigger signal is generated by block 11, depending on the selected trigger criteria.

The device works as follows.

The input signal is fed simultaneously to the input of the scaling unit 1 and to the input of the starting unit 11. When the launch requirements are met, the start-up unit 11 generates a signal that triggers the delay unit 12. The scaling unit 1 performs a scale conversion of the input signal. The signals of the same form come from its outputs to the inputs of the 2-C delay lines and to the inputs of the block 9 for overload fixation. Delay lines 2-4, controlled by the clocking pulses from block 8, synchronously advance the input signal from the input of the delay lines to their output. By the time a pulse signal appears at the output of the 2-D delay lines, the delay block 12 generates a control signal for the generator block 8 and the decoder 10. The decoder 10 converts the state of the band 9 block of the overload of the ranges to a form suitable for controlling the switch 5 and writing to the memory block 7- The state of fixing block 9 is formed during the entire time that the input signal passes through the delay lines 2-4.

The state of block 9 is depicted as a code in which the range exceeding is indicated by one, and the absence of the excess by zero. The first zero after a set of units indicates the range in which the entire implementation of the input process is best located. The decoder 10 on the location of this zero forms in the form of a code the number of the best range.

The code by the decoder 10 is fed to the input of the storage unit 7, where it is recorded by a signal from the delay unit 12. By the same signal block

7 begins registering information from the analog-digital converter 6. Since switch 5 is controlled by code, decoder 10, a signal from the delay line in which the value of the input signal best meets the input range of the analog signal is transmitted to the output of switch 5 digital conversion 6, i.e. the registrar as a whole. Signals from the remaining delay lines are canceled. The information output from the selected delay line is performed in time with the pulses of the generator block 8, the period of which changes when the delay block 12 is triggered. Thus, information is recorded in the delay lines at one frequency, and output through a com (Mutator 5 can be carried out on the other, while ensuring the transformation of the registered process over time without changing its shape. The latter makes it possible to drastically reduce the speed requirements of the analog-to-digital 6 transducer.

When the storage unit 7 is filled, the registration is stopped, and the input process and the number of the range in which the measurement was made is registered in it.

The device provides an optimal selection of the measurement range with a volume of additional information about the states of the ranges, reduced to one range number, due to the fact that the optimization of the range is carried out throughout the implementation of the input signal. The speed of the device is determined by the speed of the analog-discrete delay lines. As a consequence, the device may convert the input

quantization frequencies up to 10 MHz and more

Claims (1)

1. Mishchenko B, G. Automatic attenuator for recording amplitude and pulse shape. - Instruments and Experimental Technique, 1973, No. (prototype).