SU1302303A1 - Function generator - Google Patents

Abstract

The invention relates to analog and analog-digital computing and can be applied in the simulation of automatic control systems. The purpose of the invention is to improve accuracy. The functional converter contains an analog-to-digital converter 1, an addressing device 2, a memory block 3, five multiplying digital-to-analog converters 4-8, a memory register 9, a output adder 10. In the converter, a given function is represented by a set of discrete values fj (x), where i is the number of the split interval of the OX axis. In this case, it is assumed that the splitting intervals are the same, i.e. uses the uniform law of partitioning the axis of the argument. Discrete values of f; (x) / i and f, .x) are written to the zones of memory block 3, which are extracted in pairs when X passes to the next inte () shaft. 1 il. (L

Description

t13023032

This invention relates to the analog range of the multiplier used.

and analog-to-digital computing, they should be submitted to older

technology and can be applied in terms of the DAC, assuming that the rest

modeling of automatics contain logical zeros. regulation. 511

The purpose of the invention is to increase the exact point. The coefficients r and -j- are constant.

“Predetermined values and

The drawing shows the structure- are implemented in the circuit as a coefficient of the functional conversion circuit, transmission of the output adder 10

spinner

by the corresponding inputs.

Functional transducer co. The operation of subtracting the value holds analog-to-digital converter 1, device 2 for addressing, block 1 flixl () is realized by connecting 3 memories that multiply the digital-to-i channel i

4-8 output converters (DACs), the output of multiplying DAC 7 to memory 9 memory and the output adder. 10. The inverting input of the output sum. Functional converter 10 (input resistors and

bots as follows. feedback of the output adder

The specified function is not shown).

a set of discrete values 20 The initial value of the function f ()

, f (x), where i is the interval number divided by the converter preparation mode

Yen axis OX. It is assumed that the work is recorded in parallel.

that the split intervals are the same, binary code into memory register 9,

those. a uniform one is applied, multiplied by multiplying the DAC 8 in anorazbeni argument axis. The log signal is sent to the direct

In the zone of the memory block 3, the input of the output adder 10 is recorded at any

. . x values When using micro I lvJ v

discrete values, and a D / A circuit containing an embedded re. gistr, entry of initial value

which are extracted in pairs when the function is transferred, is performed directly by the argument x to the next inter-register. shaft.

In each section of the partition, the argument of the invention the function is represented by a segment

parabolas passing through points f ,. , es - “g

(), f (x) u, h, (x). Equation Functional Converter,

  The V-containing analog-to-digital disjoint parabola looks like

a user whose input is an InS H-1 filsl 1) with a functional functional input

SR X / -, X .l l X XXj /

 hi h 1 + 1. converter, group of senior times. f. f h series of multi-bit analog-rj-x (x-xj), digital converter is connected.

, - to the input of the addressing device ,, outputs

where -X: is the length of the interval split- “r -,

 which are connected to the address input of the x-axis of the argument .- ..

„„ Memory unit, digital inputs transition analog signal in analog,

  , second and second multiply digital-to-analog converter 1 transform

Bend converters are connected into binary code. group of old- „„

Responsibly with the first and second groups of which bits are used. - ± -

“T memory block outputs, output one

to form in the device 2

multiplying the digital-to-analog conversion of address signals by which l

 The user is connected to the direct input.

one-output adder is extracted from memory block 3, the output of which

f; (x) fii (x) is the output of the functional transient signal -t- and -v-t-. Corpse - 11 + 1 formers, different

The paired bits of the binary code, in that, in order to increase the accuracy corresponding to the increment x-x-, the memory register is inserted into it, connected to the digital inputs of the multipliers. the fourth, fifth and fifth multiplying GAL 6 and 7. In the case that the number of digital-to-analog converters, the digit of these bits does not correspond to the bit inputs of the third and fourth

313023034

multiplying digital-analogue conversion adder, analogue input of the connectors are connected to the group of lower-order multiplying digital-analogous digits of the multi-digit output of the analogue connected to the reference-digital converter bus, voltage, the output is connected to the input the inputs of the third and fourth 5 to the direct input of the output adder, and the multiplying digital-analogue digital conversion input connected to the output of the relays connected to the outputs of the corresponding memory register, the analog inputs of the first and second multiplying both the second and the second multiplying digital-to-digital-to-analogue converters, and the converters are connected to their outputs, respectively, tO by the information input of the function, to the inverse and direct inputs of the output-converter.

Claims (3)

Claims 35 Functional converter containing an analog-to-digital converter, the input of which is the information input of the functional converter, a group of high-order rows of multi-bit output of an analog-digital converter is connected to the input of the addressing device, the outputs of which are connected to the address inputs of the memory block, the digital inputs of the first and second multiplying digital-to-analog converters are connected respectively with the first and second groups of outputs of the memory block, the output of the first smartly The digital-to-analog converter is connected to the direct input of the output adder, the output of which is the output of the functional converter, which differs. The invention relates to analog and analog-to-digital computing technology and can be used in modeling automatic control systems. The purpose of the invention is improving accuracy. The drawing shows a structural diagram of a functional Converter. 10 Functional Converter contains an analog-to-digital Converter 1, a device 1 f; (x) / - th? —T — x (x-x _; ), where h = x; -x · is the length of the interval of partitioning the axis of the argument χ. The input analog signal in the analog-to-digital converter 1 is converted into a binary code, the group of high-order bits of which is used to form address signals in the device 2, according to which onef is extracted from the memory unit 3; (x) f,, (x) „temporarily signals —m— and - ¥ -γ—. The group of the least significant bits of the binary code corresponding to the increment x-x ^ is connected to the digital inputs of the multiplying ones. DAC 6 and 7, in the event that the number of these discharges does not correspond to the connector, which, in order to improve accuracy " 55 it introduced the memory register, the third, fourth and fifth multiplying digital-to-analog converters, digital inputs of the third and fourth 3 13 (multiplying digital-to-analog converters are connected to the group of the least significant bits of the multi-bit output of the analog-to-digital converter, analog inputs of the third and fourth multiplying digital-to-analog converters are connected to the outputs of the first and second multiplying digital-to-analog converters, and their outputs are connected, respectively, 10 to the inverse and direct inputs 2 addressing, memory block 3, five multiplying digital-to-analog converters (DAC) 4-8, memory register 9 and output adder 10. Functional Converter operates as follows. A given function is represented by a set of discrete values, f; (x), where ί is the number of the interval for splitting the OX axis. It is assumed that the intervals of the partition are the same, i.e. the uniform law of splitting the axis of the argument is used. In the area of the memory block 3 are written f; (x) f (x) discrete values —m— and -τ-γ—> which are extracted in pairs when passing the argument x to the next interval. On each section of the partition of the argument, the function is represented by a segment of the parabola passing through the points f _o (x = 0), f; (x) and f, _{+ l} (x). The equation of such a segment of the parabola has the form Ц хχ) 1 ₍ >. hi h ² 1 + 1 03 of the 4th adder, the analog input of the fifth multiplying digital-to-analog converter is connected to the reference voltage bus, the output is connected to the direct input of the output adder, and the digital input is connected to the output of the memory register, the analog inputs of the first and second multiplying digital-to-analog converters are connected to the information input of the functional converter.