SU1254511A1 - Analog-digital incremental calculator of values of exponential function - Google Patents

Abstract

The invention relates to automation and computing and can be used in control systems and hybrid computing devices for calculating in the next mode an exponential function from an analog signal with the result presented in digital form. The purpose of the invention is to increase speed. The essence of the invention is that the device, containing a subtractive node, a digital-to-analog converter, argument adders and functions, a zero-body, a group of threshold elements, a shift block and a pulse generator, additionally introduces a memory block, an encoder and a priority block 1 silt about 5g

Description

i.1

The invention relates to automation and computing and can be used in control systems and hybrid computing devices for calculating in the tracking mode an exponential function of an analog signal with the result presented in digital form.

The purpose of the invention is to increase the speed of the calculator.

The drawing shows a functional diagram of the proposed analog-digital incremental calculator of an exponential function.

The calculator contains the subtraction unit 1, the digital-analog converter 2, the adder 3 arguments, zero. authority 4, memory block 5, encoder 6, priority block 7, group of 8 threshold elements, function adder 9, shift unit 10, pulse generator 11, input 12 Initial installation, input 13 Start-device, device input 14, argument 15 outputs and outputs 16 functions of the device.

The calculator works as follows.

Before operation, a signal is given. The initial setting is on input 12 which zeroed the adder 3 arguments and sets code 1 to the adder 9 of the function, i.e. The low-order bits and the high-order bits of the upper part of the adder 9 are zeroed out, and the lower part of the whole part of this emitter is entered. Thus, for the zero value of the argument x O in the adder 3, the unit value of the function y 1 is established in the adder 9 of the function

which for 1x1 1 contains n low, n high-order bits and two times, a number of the integer part. Block 5 of the 1-st memory contains 2p words for the selected device size n, with function codes 1n being written in the first half (page) of memory block 5 (1 + x for argument values x 2 (, 2,.,., П), and In the second half of this block, codes of the function In (1-х) are written for the same argument values. The address to one or the other half of block 5 is performed by a signal from the output of the zero-organ 4, and addressing within each half of block 5 occurs by signals from the output of the encoder 6. The signal received at input 13 of the device’s launch starts an 11 pulse generator, which produces em

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three series of pulses: the main series - on the third output, delayed by the time (t) of the recycle process in the priority block 7 - on the second output and delayed by the time (1 :,) of the transient process in the adder 9 and the memory block 5 - on the first output 11 pulse generator.

The error voltage (flU) (between the input voltage of the analog signal at the device input 14 and the feedback voltage from the output of the digital-to-analog converter 2) from the output of the subtracting unit 1 is applied to the input of the zero-body 4 and the group of 8 threshold elements. The threshold elements of group 8 are triggered when the voltage mismatch thresholds are reached, to which the corresponding threshold elements are set (for example, according to the binary law: 1, 2, 4, ... conventional units of the least significant bit 2 adders 3 arguments).

The first block, priority block 7, at the times determined by the clock pulses from the third generator output, 1 1 pulses, determines the highest weight threshold element of group 8 from among the ones triggered and feeds the signal to the corresponding input of the encoder b, at the output of which the position number is generated (bit ), in which there is a unit in the position binary code from the outputs of the priority block 7. The binary code of the position number from the outputs of the encoder 6 is fed to the control inputs of the shift unit 10, which transfers the content, the sum ora 9 functions to the input of the same adder

9 with a shift by the corresponding number of bits for summation or subtraction with the previous value of the function, the choice of the summation or subtraction operation is made by the signal from the output of the zero-organ 4, and this operation is performed

in the second cycle at the moments determined by the clock pulses from the second output of the generator 11 pulses delayed relative to the first main series by the time t,. This series also reads the code of the function En (1 + + dx) from the memory block 5 from the cell whose address is determined by the increment sign from the zero-body 4 output (the corresponding half of the memory block 5 is selected) in

31

as the high-order bit of the address, and the code from the output of the encoder 6 as the lower-order bits of the address, i.e. To increment the signal x ± 2, select the function. In (1 + 2) recorded at address T in the corresponding half of memory block 5. The code of the function In () from the output of the memory block 5 is fed to the input of the adder 3 argument, in which it is summed with the previous contents of the adder 3 argument. This operation is completed in the third clock cycle by the signal from the first output of the generator 11 pulses, on which a series of pulses is formed, delayed relative to the previous series by the second output of the generator 11 pulses by time t determined by the reading time of the code from the memory block 5. The resulting code from the output of the adder 3 argument goes to the output 15 of the argument and to the input of the digital-to-analog converter 2, in which it converts to an analog value and is fed as a feedback signal to the second input of the subtracting unit 1. Thus, at each current moment in the adder The 3 arguments are the digital code of the input analog signal.

  X -bAX - X; .- t-fn (1 s; g-h (uUVQ)

- ..

where sign luUlj is the sign of the stress of the races

. matching, and the accuracy of its presentation depends on the selected size of the adder 3 argument and block 5 of the memory.

At the same time, the current value of the exponential func tion is formed in the function adder 9.

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- + sig-u (uU) -2 З.

The computation of the current digital value of the function and the argument, up to the least significant bit 2, is performed as much as possible in n cycles, and in each clock cycle

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one pulse at each of the three outputs of the pulse generator.

Claims (1)

Invention Formula An analog-to-digital incremental calculator of an exponential function containing a subtracting unit, a digital-to-analogue converter, an argument adder, a zero-organ, a group of threshold elements, a function adder, a shift unit, and a pulse generator, the calculator's input connected to the first input of the subtracting unit connected by the second input to the output of the digital-to-analog converter, and the output to the information inputs of the threshold elements of the group and to the input of the null-organ, whose output is connected to the input of the selection of the mode of the function adder, in The higher-order outputs of which are connected to the outputs of the calculator function and to the information inputs of the shift block connected by the outputs to the inputs of the function adder, the initial setup input of which is connected to the input of the calculator's initial setting and the input of the initial setting of the argument accumulator connected to the outputs of the digital-analog converter and the outputs the argument of the calculator, and the gate input to the first output of the pulse generator connected to the input of the launch of the calculator, and the second output to page to the circumferential input of the adder, functions are also distinguished by the fact that, in order to improve speed, a memory block, an encoder and a priority block are entered into it, with the outputs of the threshold elements of the group connected to the inputs of the priority block, whose outputs are connected to the inputs of the encoder, the outputs which are connected to the shift control inputs of the shift unit and to the address inputs of the memory block, in addition to the higher-order input of the address of the memory block connected by the input to the zero-organ output, the outputs to the inputs of the argument adder, strobirtst conductive input - to the second output of the pulse generator, and a third pulse generator output is connected to a strobe input of the priority block. one Oil . Jth © f Irs f fS Compiled by PI. Firsov Editor A. Orap Tehred I. GGopovnch Order 4723/54 Circulation 671 Subscription of the USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreading Maksimishinets