SU1247904A1 - Analog-to-digital calculator of values of logarithmic function - Google Patents

Abstract

The invention relates to the field of automation and computing. The calculator contains a readout node, a digital-to-analog converter, an argument adder, a modulo-two adder, a zero-organ, a shift unit, a memory unit, a function adder, an adder, a priority block, a threshold element block; ntov, a priority encoder, and a synchronization block. The speed and expansion of the frequency range of the processed signals is achieved by using a variable step of balancing the input analog signal, which makes it possible to calculate the values of the argument and function with an accuracy of the least significant bit 2 (n-bit calculator) for a time not exceeding 3 n clock cycles calculator 1 il. with $ (L 1CE J SO

Description

one

The invention relates to automation and computer technology and can be used in control systems and hybrid computing devices for calculating in the trail mode the log function 1c (.1 + x) from an analog signal with a representation of the result in digital form.

The aim of the invention is to increase the speed and expansion of the frequency range of the signals being processed.

The drawing shows a block diagram of an analog-digital calculator of a logarithmic function.

The analog-digital calculator of the logarithmic function contains the subtracting node 1, the digital-analog converter 2, the adder 3 arguments, the modulo adder two 4, the zero authority 5, the shift unit 6, the memory block 7, the adder 8 functions, the adder 9, priority block 10 , a block of 11 threshold elements, a priority array 12, a block of synchronization 13, information input 14, outputs 15 of the calculator and start input 16.

The calculator works as follows.

Before starting work, input 16 is given a signal, which zeroed the adder 8 of the function and sets the code 1 to the adder 3 arguments, i.e. The n bits (where n is the bit of the converter 2) the younger and n bits of the senior part of the adder 3 are zeroed out, and in the low bit of the whole part of this adder one is entered. Thus, for the zero value of the argument x O, the adder 3 of the argument is set to a single value, since function 1 (1-x) for / X / 1 is calculated. Memory block 7 contains 4 n words for the selected device size n, and In the first half (page) of memory block 7, function codes are written in (1 + x) for the argument values

X 2 ,, 2, ..., n, and in the second half of this block the codes of the function In (1 - x) are written for the same values of the argument. Addressing to the same or another half of the memory block is carried out by a signal from the output of the null organ 5 (the first address bit of the block 7), and addressing within each half of block 7 occurs

one

- five

25

2479042

according to signals from the output of the sign bit of summatr 9 (second address bit of block 7) and from the other outputs of adder 9 (younger than the bit of block 7 address).

The signal arriving at input 16 triggers a synchronization block 13, which results in three series and ffly in the main series - on the third output, delayed by the transient time (t) in priority block 10, encoding element 12 and adder 9 - on the first output and the second delayed by the time (G) of the transient process in the adder 3 arguments and memory block 7 - on the second output of block 13.

The error voltage (D U) (between the input voltage of the analog 20 signal (1 + x) at input 14 and the voltage of the feedback from the output of the digital analog converter 2 from the output of the subtracting node 1 is fed to the input the zero-organ 5 and the inputs of the block 11 threshold elements. The threshold elements of block 11 are triggered when the voltage reaches the mismatch of the threshold values to which the corresponding threshold elements are set (for example, according to the binary law: 1,2, 4, ..., 2 conventional units low-order 2 adder 8 function). In the first clock cycle, the priority At the time point determined by clock pulses from the third output of the synchronization unit, the sixth unit 10 determines the weight threshold element of unit 11 from the number of triggered and outputs a signal to the corresponding outputs, where the unit position (discharge) number is formed in the positional code of the highest triggered threshold element of block 11. This positional dual code is the input signal increments, rounded to a value that is a multiple of two, i.e. represent one unit in the corresponding bit category 50 (position code). In the same cycle, the encoder 12 determines in a similar way the number of the highest unit in the code of the adder 3 arguments, i.e. the highest unit of the TSI is selected from the code of the highest n bits of the number in the adder 3 of the argument and the binary coding of its number. As the encoder 12 can be used

thirty

A standard chip of type 100 IW 165 or K 500 IW 165 is a coding element with priority. From the binary code of the position number, the code generated by the encoder 12 is subtracted from the outputs of the priority block 10, and the result is fed to the shift control inputs of the shift block 6, which transfers the contents of the adder 3 to the input of the same adder 3 with an offset by the corresponding number of digits for summation or subtraction with the previous function value, and the selection of the summation or subtraction operation is performed by adder 4 modulo two depending on the sign of the increment and coming from the output of the zero-body 5, and signs of the adder 3 function arguments, i.e. a summing operation is performed if both these signs are the same, or a subtraction operation for different 4 x 1 characters, and this operation is performed in the second cycle at the time points determined by the clock pulses from the first output of the synchronization unit 13 delayed relative to the first output of the synchronization unit 13, detainees relative to the first main series at the time of t. In the same series, a function 1 (1 + Dx) cell is read from block 7, whose address is determined by the sign of the increment from the output of the null organ 5 (the corresponding half of the memory block is selected, where the function In (1 + & x) is written) or In (1 - Ax) as the high-order bit of the address and code from the output of the adder 9 as the lower-order bits of the address, with the sign bit of the adder 9 being fed to the input of the second address bit of the memory block 7, i.e. to increment the signal dx

t2 selects function 1g (1 +

± 2) recorded at address i in the corresponding half of memory block 7, with each half of memory block 7 having two parts for positive and negative values of the increment ratio

(2-) and addressing to the corresponding part is produced by the second most senior address bit of memory block 7. Code

the function In (1 ±) from the output of the memory block 7 is fed to the input of the adder 8 of the function, where it is summed

479044

with the previous contents of the adder 8 functions. This operation is performed in the third clock cycle by a signal from the second output of the synchronization unit 13, on which a series of pulses is generated, delayed relative to the previous series by the first output of unit 13 for a time T determined by the time the code is read from memory unit 7.

jQ The resulting code. from the output of the adder 3, the argument is fed to the input of the digital-to-analog converter 2, where it is converted to an analog value and fed as a signal

and feedback to the second input of the subtracting node 1.

Calculation of current digital characters. argument and function D1I is produced in three cycles, and the value

2Q possible increments of the argument and, accordingly, the function can be quite large. For the maximum value of the input signal, the calculation of the values of the argument and the function with an accuracy of up to the least significant bit 2 is performed in no more than 3 n cycles, which ensures an increase in the speed of 30

2 (and an average of -2 and

expansion of the frequency range in

: in .2 p / 3 times.

Claims (1)

Invention Formula An analog-to-digital calculator of a logarithmic funktsi containing a subtractive node connected by the first input to the information input of the calculator, the second input to the output of the digital-to-analog converter, and the output to the input of the zero-organ and inputs of the block of threshold elements, the argument adder connected to the inputs digital-to-analogue converter and informational inputs of the shift unit, and informational inputs — with the outputs of the shift unit, and the synchronization unit, connected by the first output to the gate input of the adder ap umenta and the input to the start of the calculator and the inputs of the initial setting of the adder of the argument and the adder of the function whose outputs are the outputs of the calculator, characterized in that, in order to improve the speed and expansion of the frequency range of the processed signals, a memory block, a priority encoder are entered into it, modulo two, priority block and adder, the outputs of the block of threshold elements connected to the inputs of the priority block connected by the outputs to the first group of inputs of the adder connected to the second group oh inputs. with the outputs of the priority encoder, and outputs with the shift control inputs of the shift unit and the address inputs of the memory unit whose outputs are connected to the information inputs of the function adder connected by the building input to the second output of the synchronization unit connected to the gate the entrance Compiled by S.Kazinov Editor N.Gorvat Tehred M.Hodanich Proofreader V. But ha Order 4128/50 Circulation 671 Subscription All-Russian Institute of Scientific and Technical Information, USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35 113035, Moscow Production and printing company, Uzhgorod, st. Project, 4 the memory block, and the third output to the gate input of the priority block and the gate input of the priority encoder, the information inputs of which are connected to the outputs of the argument adder, connected to the output of the sign bit to the first input, of the modulo adder two connected by an output to the control input of the summation accumulator of the argument adder, and the second input to the output of the null organ and the input of the first address bit of the memory block, connected by the input of the second address bit to the output of the sign bit of the adder.