SU1113820A1 - Increment multiplier for analog signals - Google Patents

Abstract

The INCREMENT MULTIPLE of ANALOG SIGNALS contains two analog-digital converters of the following type with variable balancing pitch, the first of which is connected by an information input to the input bus of the first factor, a clock input with the input clock of pulse pulses and with the trigger input, output of a sign and a clock input of a clock pulse, and with a trigger input, a sign input with a clock input pulse bus, and with a trigger input, a sign input with a clock input pulse bus, and with a trigger input, a clock input with a clock input pulse bus and a trigger input, a clock input. the balancing code - with the first input of the first modulo two, and the output of the mismatch sign - with the first input of the second modulo two, connected by the second input to the output of the sign bit counterbalance code of the second analog-to-digital converter of the next type with variable balance step, connected by the output of the mismatch sign with the second input of the first modulo-two, information input - with the input bus of the second factor, and a clock input - with the trigger output, and a shift block . connected by outputs to the first group of inputs of an adder connected by a second group of inputs to outputs of an output register, characterized in that, in order to increase the speed of an incremental multiplier, an additional adder and a shift block connected by information inputs to the codes of the second analog-to-digital converter code are entered type with variable balancing step, in addition to its sign bit, the control inputs to the outputs of the increment code of the first analog-digital pre tracer (L type with variable balancing step, a outputs - to the first group of inputs of an additional adder connected by a second group of inputs to the outputs of the main adder, control mode input with the output of the second modulo two, and outputs with information inputs of the output register connected to the clock input to the trigger code, the output of the first modulo-two adder is connected to the control input of the operating mode of the main adder, and the outputs of the balancing K.1da of the first en A sero-digital servo converter with variable balancing pitch, in addition to its sign bit, is connected to information inputs of the main shift unit connected by control inputs to the outputs of the increment code of the second analog-digital semiconductor transducer with variable balancing pitch.

Description

 i

The invention relates to computing and can be used in analog-digital and hybrid computing devices, as well as in specialized computational devices with various forms of information representation for multiplying analog signals with numerical result representation.

 A device for multiplying analog signals with a digital output is known, comprising two analog-to-digital follow-type converters, a switch, an adder-subtractor and control elements tl3.

The drawback of the device is the limited frequency range of the multiplied analog signals.

It is also known to have an analog-digital multiplying device containing an accumulating adder, a switch, a combinable adder, a group of OR elements, two blocks of a code for sequential approximation, a pulse distributor, and two analog-digital 1: converters, each of which contains a comparator, a digital-analog converter, and a register of sequential approximation 12.

This device is characterized by reduced speed.

Closest to the invention is an incremental multiplier of analog signals, containing two analog-digital follow-type converters with variable balancing pitch, the first of which is connected by an information input to the input bus of the first multiplier, a clock input and a trigger input, the output of the sign bit, the balancing code — with the first input of the first modulo-two adder, and the output of the mismatch sign — with the first input of the second adder modulo two The second input to the output of the sign bit of the balancing code of the second analog-to-digital converter of the next type with a variable pitch leveling connected by the output of the error sign to the second input of the first modulo-adder, the information input to the input bus of the second multiplier, and the clock input with trigger output, and block shift.

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connected by outputs to the first group, inputs of a combinational adder connected by a second group of inputs to the outputs of the output register, 5 connected by a control input to the clock pulse input bus and to the control inputs of the first and second analog-digital converters, and information inputs to the outputs of a combinational adder connected by a control input to the output of the first switch, connected by information inputs to the outputs of modulo-two adders, and control inputs to the control inputs of a second first and third switches and to the trigger outputs, the shift block is connected to the information and control inputs to the second and third switches, respectively, the first and second groups of information inputs of the second switch are connected to the balancing code outputs of the first and second analog-to-digital converters, respectively, except for sign bits, and the first and second groups of information inputs of the third switch are connected to the outputs of the increment codes of the first and second analog-digital conversion telephones, each of which contains a group of threshold elements connected by inputs to the output of the subtracting node, and outputs to information inputs of the priority block connected by a clocking input to the clocking input of the accumulating Adder, and outputs to outputs of the increment code of the analog-to-digital converter and with information inputs of the accumulating adder connected by a control input to the output of the zero-organ, and the outputs of the bits to the inputs of a digital-to-analog converter connected by the output with the first input to the reading node, the second input of which is an information input of the analog-digital converter, and the output is connected to the input of a zero-body, the output of which is the output of the error sign of the analog-digital converter, and the discharge outputs of the accumulating adder, including its significant digit, outputs of the balancing code of the analog-to-digital converter.

3

The disadvantage of the prototype is reduced speed, due to the fact that it takes two cycles of operation to obtain one multiplication result.

The purpose of the invention is to increase the speed of an incremental multiplier.

The goal is achieved in that in an incremental multiplier of analog signals containing two analog-digital converters of the following type with variable balancing step, the first of which is connected by an information input to the input bus of the first factor, and the clock input is connected to the input pulse bus and to the trigger input ,

 the output of the sign bit of the balancing code is with the first input of the first modulo-two adder, and the output of the mismatch sign is with the first input of the second modulo-two adder connected by the second input to the output of the sign bit of the balancing code of the second analog-to-digital converter of the next type with variable the step of balancing connected by the output of the mismatch sign with the second input of the first modulo-two adder, the information input - with the input bus of the second factor, and the clocking input - from the output trigger trigger, and a shift block connected by outputs to the first group of inputs of an adder connected by a second group of inputs to the outputs of the output register, an additional adder and a shift block are added that are connected by information inputs to the outputs of the second-to-digital converter of the following type with a variable balancing step besides its sign bit, the control inputs are connected to the outputs of the increment code of the first analog-digital converter of the next type with variable balancing step, and outputs to the first group of inputs of an additional adder connected by a second group of inputs to the outputs of the main adder, an input for controlling the operating mode — with the output of the second modulo-two adder, and outputs to the information inputs of the output register connected by a clock input to the trigger output,

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the output of the first modulo-two summator is connected to the control input of the operating mode of the main adder, and the outputs of the balancing code of the first A / D converter of the next type with a variable balance step, except for its sign bit, are connected to the information inputs of the main unit

the shift connected by the control inputs with the outputs of the increment code of the second analog-to-digital converter of the next type with variable balancing step.

FIG. 1 shows a block diagram of an incremental multiplier for analog signals; in fig. 2 is a possible embodiment of the block diagram of each of the analog-to-digital converters

tracing type with variable balancing step.

The incremental multiplier of analog signals contains the first and second analog-to-digital converters 1

and 2 of the following type with variable balancing pitch, the main and additional blocks 3 and 4 of the shift, the main and additional adders 5 and 6, the output register 7, the first and second adders 8 and 9 modulo two, the trigger 10, the first factor input bus 11 , bus 12 input of the second factor, outputs 13 incremental multiplier, bus 14 initial installation and bus 15 input

clock pulses. Each of the analog-digital converters 1 and 2 (Fig. 2) contains (similarly to the prototype converters) subtractive

node 16, group of 17 threshold elements, priority block 18, accumulating adder. 19, a digital-to-analog converter 20 and a null-body 21. An incremental analog multiplier

The signals works as follows.

The initial setup signal from bus 14 clears the A / D zero state.

converters 1 and 2 (accumulating adders 19, which are included in them) and output register 7. When analog signals are connected to input factor buses 11 and 12 and clock pulses are applied to bus 15, the first analog-to-digital converter 1 is started and with a delay of one clock through trigger 10 51 (type D) of the second analog-to-digital converter 2. The analog-to-digital converter (Fig. 2) works as follows. The initial setup from bus 14 is reset to the accumulating adder 19. From the bus 11, an analog signal is connected from the bus. 15 — clocking pulses. The subtracting node 16 determines the difference between the input voltage and the counterbalancing voltage of the reverse connection from the output of the digital-to-analog converter 20, which is an application. to the input of the zero-organ 21 and the inputs of all threshold elements of group 17. Sign-sensitive threshold elements are triggered when the voltage reaches the difference between the threshold values that are tuned (for example, according to the binary law: 1, 2, 4, ..., 2 conventional units where m is the number of elements of the group). The priority block 18 at the times determined by the clock pulses is selected by the highest-weight threshold element among the ones triggered. At the same time points, the zero-body 21 determines the sign of the difference voltage, which is a signal. The mismatch of the analog-to-digital converter. Codes with. the outputs of priority block 18 are input signal increments rounded to a multiple of a power of two, i.e. are one unit in the corresponding code bit (position code). The output codes of priority block 16 are the signal of the increment code of the analog-to-digital converter. The code of the sign of the voltage difference from the output of the null organ 21 sets the accumulating adder 19 to the control input for performing the operation Addition or Subtraction. At the times determined by the clock pulses, the accumulating adder 19 adds or subtracts from it the unit of the corresponding bit received from the priority block 18. VELOCUSES of the accumulating adder 19 are outputs of the balancing code of the analog-to-digital converter and control the digital-analogue converter 20, striving to reduce the amount of mismatch between the input voltage and the feedback voltage 06 from the output of the digital-to-analog converter 20. An analog-to-digital converter detector 2 is completely analogous to analog-to-digital converter 1. Balancing codes from the outputs of the First 1 and second 2 analog-to-digital converters (except for bits of bits) are shifted under the control of the outputs of the increment value of the second 2 and first 1 analog-to-1 converters of the converters and go to the corresponding group inputs of the main 5 and additional 6 supervisors. The first 8 and second 9 modulo adders analyze the sign of the output code of one analog-to-digital converter and the increment sign of the other and control the mode of operation (Addition or Subtraction) of adders 5 and 6. The modulo adder outputs the code O (Addition) with equal signs and code 1 (Subtraction) with different signs. Thus, in each cycle of operation of the multiplier, the output code of the first analog-to-digital converter 1 is added to the contents of output register 7, shifted by the number of bits corresponding to the increment value of the second analog-digital converter 2, and the output code of the second one delayed by one clock analog-to-digital converter 2, shifted by the number of bits corresponding to the increment value of the first analog-digital converter 1, in the output register 7 after each clocking pulse of fixed current code value of the product of two analog signals, which is supplied to the outputs 13 of the device. The multiplier operation algorithm can be described by the following expressions: X, .х, -axil 4m 4 1 - operations are useful. y - i ftV- (t - f h) s in analog-digital converters 1 and 2 i - Y 1 Y; (signx, @ signfty) / Х4и // 4У1 / (signy- @ signuXi) / у {// ftx /, where x, y. and x, y are digital input values: signals at times t and t ,;

AX; j And Lou - increments

input signals over time

  , tb. ; Ay.2; Oik in-1;

® - modulo 2 summation operation;

 - modulus of x ;.

. The three terms in the last expression are summed on adders 5 and 6, per cycle of operation, while in the prototype analog-to-digital converters work alternately, and

The calculation of the new product of signals is carried out in two cycles of operation. In this case, although an additional adder is included in the considered multiplier, however, delays in the switches are excluded, in connection with which the length of the combination chain for one clock cycle remains approximately the same.

Thus, the proposed multiplier provides 2 times faster response than the prototype, which determines the technical and economic advantage of its possible use.

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fie.g

ftS / f.8 tf OL. 3

Claims (1)

An incremental multiplier of analog signals, containing two analog-to-digital converters of a tracking type with a variable balancing step, the first of which is connected by an information input to the input bus of the first multiplier, a clock input - to the input bus of clock pulses and to the input of the trigger, the output of the signed digit the first input of the first adder modulo two, and the output of the mismatch sign - with the first input of the second adder modulo two · connected by the second input to the output of the sign bit Yes, the balancing code of the second analog-to-digital converter of the tracking type with a variable balancing step, connected by the output of the error sign with the second input of the first adder modulo two, the information input - with the input bus of the second factor, and the clock input - with the output of the trigger, and a shift unit connected outputs to the first group of inputs of the adder connected by a second group of inputs to the outputs of the output register, characterized in that, in order to increase the speed of the incremental multiplier, into it additional adder and a shift unit are connected, connected by information inputs to the outputs of the balancing code of the second analog-to-digital converter of the tracking type with a variable balancing step, except for its sign discharge, control inputs to the outputs of the increment code of the first analog-to-digital converter of the tracking type with a variable balancing step, and outputs - to the first group of inputs of the additional adder connected by the second group of inputs to the outputs of the main adder, the mode control input · with the output of the second adder modulo two, and the outputs with information inputs of the output register connected by a clock input to the trigger output, the output of the first adder modulo two connected to the control mode input of the main adder, and the outputs of the balancing code of the first analog-digital a tracking type converter with a variable balancing step, in addition to its significant discharge, is connected to the information inputs of the main shift unit connected by the control inputs to the outputs of the code rashchenija second analog-to-digital converter follower type with variable pitch equilibration. η 1113820 connected by outputs to the first group, inputs of the combinational adder, connected by a second group of inputs to the outputs of the output register, 5 connected by a control input to the input bus of the clock pulses and to the control inputs of the first and second analog-to-digital converters, and information inputs - to the outputs of the 10 combination an adder connected by a control input to the output of the first switch connected by information inputs to the outputs of the adders modulo two, and by controlling 15 inputs to the control input m second and third switches and to the outputs of the flip-flop, wherein the shift unit is connected informational