SU1175034A1 - Residual glass system code-to-voltage converter - Google Patents

Abstract

1. THE RESISTANT CLASS SYSTEM CODE CONVERTER, containing n registers, according to the number of bases of the system of residual classes whose inputs are converter input buses, the outputs (l -1) of registers are connected to the corresponding first inputs (p-1) of comparison blocks, direct outputs of which are connected to the inputs of the comparison signal assembly unit, the first output of which is connected to the control input of the voltage output unit, the output of which is the output bus of the converter, the input is connected to the output of the summation unit voltage, the first input of which is connected to the output of the first digital-analog converter, characterized in that, in order to increase speed, it has (a -1) adders modulo the bases of the system of residual classes, except the smallest, the first and second code converters, (-1) elements AND, (n-1) counters, (and-1) digital-analog converters, key block, control block, the first input of which is combined with the control input of the key block and is the start conversion bus , the second input is connected to the first output in the comparison signal assembly unit, the group of second outputs of which and the inverse output of the first comparison block are connected to the corresponding first inputs of the first code converter, the second inputs of which are connected to the corresponding direct outputs of the comparison blocks, the third input is connected to the first output of the control unit, and the outputs corresponding to the first inputs of the second converter codes and the first inputs of the corresponding (t--) elements And. The second inputs of which are combined with the control inputs of the modulators are connected to the second output of the control unit, the outputs are connected to the inputs (p-1) of the counters, the outputs of which are connected to the corresponding inputs of the corresponding (p-1) digital-analog converters, the outputs which are connected to the corresponding (p-1) inputs of the voltage summation block, while the outputs of the first register are connected to the corresponding inputs of the first digital-to-analog converter and to the corresponding inputs of the key block, the outputs of which They are connected to the respective second inputs of the second code converter, the outputs of which are connected to the corresponding information inputs of the modulators whose outputs are connected to the corresponding second inputs of the respective comparison blocks. 2. The converter according to claim 1, characterized in that the unit

Description

control is complete on clock generator, AND element, Trigger element, delay element whose input is the first input of the control unit, the output is connected to the S input K5 of the trigger, whose K input is the second input of the control unit output is the first output of the block control and connected to the first input element And, the second input of which is connected to the output of the clock generator, and the output is the second output of the control unit. 3. The converter according to claim 1, characterized in that the comparison signal assembly unit is made on (n-2) AND elements, the first inputs of which and the second input of the first AND element are the inputs of the comparison signal assembly unit, each direct output (n 3) And elements, starting from the first, are connected to the second input of the subsequent AND element, the direct output (and 2) of the AND element is the first output of the comparison signal assembly unit, and the inverse outputs of the AND elements are the second outputs of the comparison signal assembly unit.

The invention relates to computing technology and can be used to interface computing devices operating in residual class systems (JUICE) with different terminals, requiring analog output, as well as in communication technology when using JUICE in digital telephony. The purpose of the invention is to transform the conversion. FIG. a block diagram of the converter of the CS in voltage is given; in fig. 2 - an example of the implementation of the first and second converts. code readers for the base SOK 2, 5, 7. The converter of the code JUICE to voltage contains adders 1.1 - 1 fi modulo SOK except the smallest, registers 2.1 - 2.P, blocks 3.1 3, l-1 comparison, unit for assembly of comparison signals which is performed on elements AND 4.1 - 4 p-2 first and second converters 5 and 6 codes, block 7 keys, control block 8, which is executed on delay element 9, RS - trigger 10, element 11, generator 12 clock pulses, elements And 13.1 - 13.P-1, counters 14.1 - 14ts-), digital-to-analog converters (D / A converters) 15.1 - 15p, block 16, voltage measurement, block 1 7 voltage output, input buses 18.1-18p, output bus 19, conversion switch 20. The first and second converters 5 and 6 codes can be implemented, for example, as shown in FIG. 2, for JUICE with base 2, 3, 5, 7 on the elements And 21.1 - 21.3 and the elements Sh1I 22.1 - 22.5, respectively. The converter works according to the following principle. The number A, represented in the JUICE by the grounds of P, P,. ., Pf ocTaTkami, dL, (1 .... In the generalized positional system (OPS), is written as follows: ...... + A, ... Finding the coefficients a, and with their help the voltage U) (AA, is is the final transformation task. Obviously, o1, / A / p / A / p / a + ajpi / p.,; PI + PiPz + a., Ptx-i / RP In other words, to find the coefficient a; the value of p until cA.j becomes equal and, therefore,. Similarly, / a, + jt jL, У 0-3

Thus, it is possible to find all the coefficients a, and then, by multiplying, by the corresponding weights, to find the value A. For multiplying in analog form, one can use digital-to-analog converters, whose quantization step is equal to

1. L, R L, V-PI Pi-fo--, u 5

Then-

JJ a, -, u-ja, p Pj ... + a ... p „., Nd A-U, i.e. conversion task solved.

The SOC to voltage converter works as follows.

In the initial state, all adders are 1.1 -1in-i; modulo m, counters 1A.1 - 14 ... .block 16 and RS - trigger 10 reset. Residues and ,, OCf are supplied to the input buses 18, and are written to registers 2.1 -2. The DAC 15.1 has a l- quantization step.

A short pulse is applied across bus 20, which opens a block of 7 keys and a code ot), the second transducer 6 passes the code is written to the adders 1.2-1. Modules. The delay element 9 is designed so that the delay of the signal in it is longer than the trigger momentum. Thus, RS - trigger 10 goes into one state after block 7 of keys is closed. A single potential from the direct output RS - flip-flop 10 is applied to the second input of an AND 21.1 element, to the first input of which a single potential is fed from the inverse output of the comparison unit 3.1. Under the action of the signal from element 21.1 in the second transducer 6 of the code, a code of the value P ,, is formed. At the same time, a single potential from element 211. 1 is fed to the first input of element 13.1 and thus allows the passage of clock pulses from control unit 8. Under the action of each clock pulse, all accumulators 1.1-1 p-1 are added. Counter 14.1

mask

one1 temporarily increases your condition

by 1. The moment when. becomes ix, i.e. equality is fulfilled

 + JPf / pt 2 J counter 14f will contain the value a „, which, having passed the process of the digital-to-analog converter in - DAC 15.2, having a quantization step p, will be written into block 16 as the value a p, & and add up to a, e. If the codes of the OS 2 and the contents of the adder 1 {modulo the direct output of the block 3.1 coincide, the unit potential and in the inverse zero. As a result, the output of the element And 21.1. the unit potential disappears, and the output of the element 21.2 goes to one input of which is supplied the unit potential from the direct output of block 3.1, and the other potential from the inverse output of the element 4.1, to the zero potential. Passing pulses is now resolved to the counter 14.2, and adders 1.2 1.1 (1-1 for each clock cycle the value P ,, P is added, the code of which is now formed at the output of the second converter 6 of the code. When of., Becomes equal toixf, the output of the next element I will be switched again. And the first converter of the 5th code, and in block 16 the value a will be added, p r d. Then the process will be continued until the output of the element 4 is. unit potential. By this time in block 16 there will be a value

Ux L (a, + a p +.. + A p p ...,

) AA

P: h.

: h-1

The unit potential at the output of the element 4. And., G | -2 will switch the RS - trigger Y to the zero state, which will detect the issuance of clock pulses from the control unit 8 and open the voltage output unit 17, the result of the conversion will be read out via the bus 19.

h /; Z /.../ J

FIG. 2

Claims (3)

1. RESIDUAL CLASS SYSTEM CODE CONVERTER IN VOLTAGE, containing η registers, by the number of bases of the residual class system, the inputs of which are the input buses of the converter, the outputs (Λ -1) of the registers are connected to the corresponding first inputs (p-1) of the comparison units, direct outputs which are connected to the inputs of the unit for assembling the comparison signals, the first output of which is connected to the control input of the voltage output unit, the output of which is the output bus of the converter, the input is connected to the output of the summing unit i, the first input of which is connected to the output of the first digital-to-analog converter, characterized in that, in order to improve performance, it includes (i -1) adders for the base modules of the system of residual classes, in addition to the smallest, perry and second code converters, ( p-1) AND elements, (p-1) counters, (p-1) digital-to-analog converters, a key block, a control block, the first input of which is combined with the control input of the key block and is the bus to start the conversion, the second input is connected to the first cig assembly block output comparison channels, the group of the second outputs of which and the inverse output of the first comparison unit are connected to the corresponding first inputs of the first code converter, the second inputs of which are connected to the corresponding direct outputs of the comparison blocks, the third input is connected to the first output of the control unit, and the outputs to the corresponding first inputs of the second code converter and the first inputs of the corresponding (n-1) AND elements, the second inputs of which are combined with the control inputs of the adders by modules and connected to the second output of the unit As controls, the outputs are connected to the inputs (p-1) of the meters, the outputs of which are connected to the corresponding inputs of the corresponding (p -1) digital-analog converters, the outputs of which are connected to the corresponding (p-1) inputs of the voltage summing unit, while the outputs of the first of the register are connected to the corresponding inputs of the first digital-to-analog converter and to the corresponding inputs of the key block, the outputs of which are connected to the corresponding second inputs of the second code converter, the outputs of which are connected to the corresponding their data inputs of adders modules vyhodykotoryh podklyuchenyk respective second inputs of the corresponding comparators. 2. The converter according to π. 1, characterized in that the control unit is made on a clock, element And, RS trigger, delay element, the input of which is the first input of the control unit, the output is connected to the S-input of the RS-trigger, the R-input of which is the second input of the control unit, the output is the first output of the control unit and is connected to the first input of the And element, the second input of which is connected to the output of the clock generator, and the output is the second output of the control unit. 3. The converter according to claim 1, characterized in that the comparison signal assembly block is made on (i-2) AND elements, the first inputs of which and the second input of the first AND element are inputs of the comparison signal assembly block, each direct output (p-3) And elements, starting from the first, is connected to the second input of the subsequent And element, the direct output (p- 2) of the And element is the first output of the comparison signal assembly, and the inverse outputs of the And elements are the second outputs of the comparison signal assembly.