SU1396280A2 - Binary code-to-binary-decimal code of angular units converter - Google Patents

Description

15

The invention relates to automation and digital computing, can be used in the construction of transducers in measuring and control systems, and is additional to auth. St. No. 970354.

The purpose of the invention is to increase the speed of the converter. jg

Figure 1 shows the structure - converter circuit; 2 shows an exemplary embodiment of functional schemes of blocks 14 and 10.

The Converter contains (1) pulse generator 1, the first element And 2, the binary counter 3, information input 4, the decoder 5, the adder 6, register 7, the input 8 of the task constant, the second element And 9, binary-2d-decimal counter 10, output P, third element I 12, additional binary counter 13, block 14 of managing — converting the higher bits of the input code.

Functional diagrams of blocks 14 and 10 for one version (Fig. 2) - contain a decoder of 15 pulses, two and four input elements OR 16 and 17, a pulse frequency divider 18 containing an AND 19 element and a three-digit binary counter 20, as well as Block 10 — four binary decimal 21, two binary hexadecimal 22, and one binary 23 pulse counter and four two-input 35 or 24 elements.

The Converter operates as follows.

At the beginning of the conversion cycle, the register 7 is cleared, the binary-decimal counter 10, the additional binary counter 13 (these circuits are not shown) and information input 4 to the binary counter-controller 25

thirty

decoder 5 enters resolving potential at the second input of the element and pulses of the generator 1, arrives at the first input of the element AND 2, passes through the element AND 2 and enters the input of the subtraction of the lower bits of the binary counter 3, at the first input of the element AND 9 and at the clock in register 7.

An adder 6 closed in a ring 6 represents the accumulating adder, which adds a binary constant integer constant C, written in input 8, to the clock clock to the second clock pulse. The value of the constant C (binary equivalent of the lowest-order bit the input code Nj is chosen from the condition of excluding the error and provides the formation of transfer at the output of summat 6 at the moments of time when the fractional sum of the fractional frequencies of the code Nj equals the whole angular unit - the weight of the youngest bit of the output binary code etchika 10. Signal lane meat arising summato outlet 6, after a number of cycles of complements adder 6 permits direct pulses circulated through the element to a summing input binary-ten counter 10 t Nogo.

At the same time, with the arrival of the generator pulse from the output of the element I 2 to the input of the subtraction of the lower bits of the binary counter 3, the code at the output of the lower bits of the counter 3 decreases by one. By passing pulses, the smallest times of register-counter 3 come to the left state and the first output of the encoder 5 is removed, the resolution of the input and the element is removed. And 2. The test is completed

the gistr 3 records the input number N 45 a lower code conversion

in the form of an n-bit binary code angle. The older bits of the binary counter 3, having predominantly weights corresponding to integer degrees, minutes and seconds of the part N ,, input - the 50th code N, and the lower N, j bits of the same counter 3, having weights with fractional parts of seconds and forming the rest of the N input number N, have separate counting inputs. At 55 this is K s + P1 + n-1.

If the code of the least n bits differs from zero, then from the first output

d

five

five

0

the decoder 5 receives the resolving potential at the second input of the element AND 2 and the pulses of the generator 1, which arrive at the first input of the element AND 2, are passed through the element AND 2 and enter the input of the subtraction of the lower bits of the binary counter 3, to the first input of the element 9 and the clock register input 7.

Ring-closed adder 6 and register 7 represent the accumulating adder, which for each clock pulse adds to the binary number recorded in register 7 the integer constant C, formed at input 8. The value of the constant C (binary equivalent weight of the least significant bit of the input code Nj) is selected from the condition of excluding the incident error and ensures the formation of the transfer at the output of the adder 6 at the moments of time when the partial amount of the fractional frequencies of the code Nj is equal to the whole angular unit - the code low output binary decimal 10. The transfer signal that occurs at the output of the adder 6, after a certain number of cycles of filling the adder 6 allows the passage of pulses through the element 9 to the summing input of the binary decimal 10.

At the same time, with the arrival of each generator pulse from the output of the element AND 2 to the input of the subtraction of the lower bits of the binary counter 3, the code at the output of the lower bits of the counter 3 decreases by one. After the pulses have passed, the lower bits of the register-counter 3 are brought to the zero state and the first output of the decoder 5 is cleared at the input and the element. And 2. The conversion of the low-order code is completed.

the bits of the input number to the unitary code is the number of pulses N, multiplying it by the constant C and converting the integer part of this product to the output binary-ten angle code. The time for converting the number N written in lower order is defined by the expression

T sN-T GP li-l Z r

where t, - pulse repetition period

generator 1.

Simultaneously with the beginning of the conversion of the lower bits of the input code

the numbers Nj the conversion of the number N ,, recorded in the high-order bits of the binary counter 3 begins. With the occurrence of the resolving potential at the second output of the decoder 5, the generator 1 pulses through element 12 begin to flow to the counting input of the additional counter 13, whose outputs are connected to the inputs, the conversion control unit 14 of the higher bits. For a given width n of the input angle code, the structure of block 14 depends on the division of the input code bits into higher n and lower n and is determined by the number of units in each decimal representation of the weight of the lower digit of the number N, For simplicity, Fig. 2 shows the functional block 14 for the particular case n, 9 with a particular structure of the binary-decimal counter 10, made for the output code degrees - minutes - seconds. The weight of the lower digit of the number N at p 9 corresponds to the decimal representation of the angle 42, II, 25, therefore, the operation of block 14 is chosen equal to ten cycles (4 + 2 + 1 + 1 rounding clock + reset clock) of the pulse generator. The main element of the block 14 (Fig. 2) is a pulse decoder, the clock input of which receives the generator pulses from the output of an I 12 element, and the information inputs receive the outputs of an additional binary counter 13. The pulses of the first four clock cycles of the decoder from the output the four-input element OR of block i 4 through the corresponding element OR of block 10 is fed to the summing input of a six-minute sextade of a binary-decimal counter. The pulses of the two following cycles arrive at the counting input of a decade of units of minutes of a binary-decimal counter. The pulses of the seventh and eighth cycles of the decoder through the elements of OR block 10 are fed to the counting inputs of a sixth-second sectade and a decade of seconds of a binary-ten counter. The pulse of the ninth cycle, to which the value of 0.25 is attributed, is sent to the input of a pulse frequency divider consisting of a three-digit binary counter and an element I. After each fourth cycle of operation of the decoder, a clock pulse appears on the output of the element And one binary counter and at the same time

0

0

5 35 Oh. 45 50 55

steps on the decade's decad unit of seconds of a binary-decimal counter (0.25x4 1). The FiMnynbc of the tenth clock of the decoder from the output of block 14 is input to the zero counter of the binary counter 3 and simultaneously to the input of the subtraction of the higher n (bits of the binary counter 3, Thus, the cycle of the block 14 contains ten cycles and for each cycle of its operation the code in the higher bits of the binary counter 3 is reduced by one. After N cycles of the block 14 n, the bits of the counter register 3 go to the zero state and the decoder 5 with its second output removes the resolution at the input of the element 12. This completes the conversion of the high n, dd s input code.

The conversion time of the number N written in the high-order bits is determined by the hyphenation

T „10..N, -Tr

p, 10-2 -T

city (2)

where JO is the number of cycles of one cycle of operation of block 14.

Since the conversion process of the higher n and the lower n bits of the input code is performed in parallel, the total transformation time T of the input number is determined not by the sum of T f and T, but by the large value of one of them.

Let us estimate for two values of the input code n 14 and n 20 the ratio of the conversion time of the known and proposed converters.

Example i. The maximum conversion time of the known transducer when the input binary code of the angle n is bounded is determined by the expression

yoke

2 -T,

214

 one ,

The maximum conversion time of the higher n bits of the proposed converter for a given case of constructing its circuit with n;, 9 is determined by the alignment (2)

t in p, max g g

In this case, the maximum conversion time of the lower n 14-9 5 bits is determined by the expression (1)

p m "ks

 ,

Since T,

T

 Make

TO maxi: the minimum conversion time of the proposed converter is determined by the expression

but

 T,

offer

TP, LLS, "10-2 -Tg

The ratio of TU-. / T

14

willow npeAl

k2 Tg 3.2. shows that the conversion time of the proposed converter: the reader is 3.2 times less than the conversion time of the known converter.

Example 2. It accepts the width of the input code of p 20. Using similar reasoning, it can be shown that the conversion time of the proposed conversion is 204.8 times less than the conversion time of the known converter.

Examples 1 and 2 show that the efficiency of the proposed converter increases with an increase in the input code width.

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Claims (2)

1. THE CONVERTER OF THE BINARY 'CODE TO THE BINARY-DECIMAL ANGULAR CODE OF UNITS according to ed. No. 970354, with the exception that in order to improve performance, the third element I was introduced into it , an additional binary counter and a high-order conversion control unit of the input code ^ where the first output of the high-order conversion control unit of the input code is connected to the summing input of the binary decimal counter, the second output ^? with a subtracting input of the upper bits of the binary counter and an input for zeroing the additional binary counter, the counting input of which and the clock input of the control unit for converting the upper bits of the input code are connected to the output of the third element And, the first and second inputs of which are connected respectively to the output of the high-order degarator and the generator output pulses, the output of the additional binary counter is connected kg. to the information input of the control unit for the conversion of the senior bits of the input code. 2. The Converter according to claim 1, characterized in that the control unit for the conversion of the upper digits of the input code contains a decoder, two OR elements and a pulse frequency divider, consisting of a three-digit binary counter and an AND element, with the gate and information inputs of the decoder connected to the clock invariant and _Q inputs formational unit 58 outputs the first four bits of the decoder are connected to inputs of first OR ,, outputs of the fifth and sixth bits of the decoder are connected to inputs of the second element IL , The outputs of the first and second members. OR, the seventh and eighth bits of the decoder and the pulse frequency divider are connected to the first output of the unit, the second output of which is connected to the output of the tenth bit of the decoder, the output of the ninth bit of which is connected to the input of the pulse frequency divider. SU „„ 1396280 - 13962802