SU1439745A1 - Binary to binary-decimal code converter - Google Patents

Description

The invention relates to automation and computing and can be used in the construction of code converters,

The purpose of the invention is to simplify the converter.

The drawing shows a block diagram of the Converter.

The converter contains a distributor of 1 pulses, a group of elements AND 2, an input register 3, a serial binary-decimal adder 4, a group of elements OR 5, elements 6 of a controlled delay — a distributor of 1 pulses, the first encoder 7, input 8 of the start of the converter, an output 9 conversion boxes, sum register 10, sum register 11, second encoder 12.

The proposed Converter works as follows.

Consider first the operation of the device, provided that in all bits of the register of the binary number 3 there are significant ones.

In this case, after the converter pulse start-up input to input 8, elements And 2 of the first group turn out to be open and pulse signals appear at their outputs, which post fall to the input of the first encoder 7. The pulse signals from the output of the encoder 7 in the form of a binary dec An ordinary code, which corresponds to the sum of the binary bits received from the outputs of the first, fourth, fifth, and six O elements And 2 of the first group, is written in parallel to the register 10 of the term. Pulse signals from the output of the encoder 12, also in the form of a binary-decimal code, which corresponds to the sum of binary bits received from the outputs of the second and third elements And 2 of the first group, are written in parallel to the sum register 11.

Thus, after the end of the start pulse, the registers of the term 10 and the sum 11 are recorded binary-decimal equivalents corresponding to the bits of the first group of input register 3.

At the same time, the signal from the output of the first element OR 5 of the group affects the first element 6 of the controlled delay so that it causes a delay in the pulse at the output of this element by the time required for summation

the data recorded in the registers of the term 10 and the sum 11, which is equal to T Nt, where N is the number of bits in the register of the term (sum), T is the period of the clock frequency supplied to the registers.

Upon receipt of clock signals | To the registers of the addendum 10 and the sum 11 in the sequential binary-decimal adder 4, a fine addition of the data recorded in registers 10 and 11 is performed. From the output of the sequential binary-decimal adder 4 the result of this addition is again recorded in the register 11 amounts. The delayed pulse from the output of the first element 6 of the controlled delay polls the bits of the input register 3 connected to the elements And 2 of the second group. From the output of the AND 2 elements of the second group, the pulse signals are sent to the encoder 7, which converts these signals, corresponding to the code of the bits of the input register 3, into an equivalent binary-decimal code, which is written in parallel to the register 10 of the term. The signal from the output of the second element OR 5 of the group provides a delay in the passage of the signal through the second element 6 of the controlled delay. During this delay, a second conversion cycle is performed, namely, the summation of the data in the registers of term 10 and sum 11. The result of the summation is again recorded in sum register 11.

In a similar way, the remaining bits of the input register 3 are transformed as the start pulse passes through the elements 6 of the control section.

Thus, when the pulse at the output of the last control delay element 6 in the sum register 11 is received, the number is written in a binary-decimal code, which is equivalent to the binary number recorded in the input register 3.

If there are no significant units in the code of the corresponding bits of the input register 3 associated with a particular group of elements And 2, then the elements of the corresponding group And 2 are closed and there are no pulse signals at their output.

At the same time, at the output of the OR 5 element of the corresponding group, under the influence of the zero bits of the input register 3, there is a logical signal O and the corresponding search element 6 of the controlled delay of the pulse distributor 1 transmits a pulse from input to output without delay.

Thus, there is an instantaneous transition to polling the next group of bits in the input register 3.

Further, a pulse without delay passes through the corresponding element 6 of the controlled delay of the pulse distributor of the first group of bits of the input register 3, in which there are no significant units, until the group with at least one significant unit is interrogated. The operation of the device in this case is similar to that described.

The binary-decimal adder, which is used in the known converter, performs the conversion by adding the correction of binary-decimal numbers by tetrads and the sequential shift (transfer) to the next binary order-decimal adder, that is, the conversion is carried out sequentially from tetrad to tetrad. As a result of the transformation inside the tetrad, correction may be made. If a transfer occurs in a tetrade, then the number six is added to it to compensate for the difference.

0

in scales of discharges. Due to this, the correct value of the binary-decimal number is achieved. However, it may still contain pseudo-tetrads. Therefore, it is checked whether the number in this tetrad is greater than nine. If so, then the number six is also added to eliminate the pseudo-tetrad. The resulting transfer, as well as the usual one, is successively transmitted to the preceding tetrad.

In the proposed converter, the number of conversion cycles is always equal to the number of groups containing significant units in the bits of the number written in the binary number register. Conversion time tnj of the proposed converter

0

tnj K T,

where K is the number of groups of binary bits in which there are

units; Tij.- one conversion time

binary bit groups Thus, in the proposed converter, the number of conversion cycles is one less than the known one.

The performance gain occurs when there are significant units in the first group of bits of the binary number register.

The distribution of bits is given in the table.

Claims (1)

Binary to decimal converter containing the input register, first encoder, binary decimal adder, pulse distributor, element groups AND, groups of η elements OR, where η is the number of groups of elements AND, the first inputs of elements AND of the j-th group ( j = 2-n) are connected to the (j-Ι) output of the pulse distributor, the clock input of which is the start input of the converter and connected to the first inputs of the elements AND of the first group, the outputs of the group of those bits of the input number register, whose weight values do not contain units in same name discharges are connected to the second inputs of AND elements of the corresponding group ·, and the outputs of the ith (i = l) group of bits of the input number register are connected to the inputs of the i-ro element OR groups, the inputs of the input number register are information inputs of the converter, the output end of conversion ·. which is the high-order output of the pulse distributor, the outputs of the AND elements of all groups except the second are connected to the corresponding inputs of the first encoder, characterized in that, in order to simplify the converter, it contains a sum register, a term register, a second encoder, and a binary-decimal adder made sequential, with the first and second information inputs of a serial binary-decimal adder connected _Λ yen with the outputs of the higher digits of the register of the sum and register of the term, respectively, the clock inputs of which and the clock input of the serial binary decimal adder are connected to the clock input of the converter, the outputs of which are the outputs of the term register, the bit inputs of the register of the term and the sum register are connected respectively to the outputs of the first and second encoders, the output of the serial binary decimal adder is connected to the input of the least significant bit register amounts, the inputs of the second encoder are connected to the outputs of the corresponding elements AND of the second group.