SU809150A1

SU809150A1 - Binary-to-bcd converter

Info

Publication number: SU809150A1
Application number: SU782651896A
Authority: SU
Inventors: Фридрих Натанович Березин; Владимир Александрович Кисурин
Original assignee: Институт Ядерных Исследований Анукраинской Ccp
Priority date: 1978-07-31
Filing date: 1978-07-31
Publication date: 1981-02-28

Description

(54) ПРЕОБРАЗОВАТЕЛЬ ДВОИЧНОГО КОДА В ДВОИЧНО-ДЕСЯТИЧНЫЙ(54) BINARY CONVERTER BINARY DECIMAL

II

Изобретение относитс к автоматике и цифровой вычислительной технике и может быть использовано при построении двоично-дес тичных преобразователей.The invention relates to automation and digital computing and can be used in the construction of binary-decimal converters.

Известен преобразователь двоичного кода в двоично-дес тичный, содержащий сдвиговый регистр, состо щий из последовательно соединенных тетрад, блоков коррекции, блоки коммутации и синхронизации 1.A binary-to-binary converter is known, containing a shift register consisting of series-connected tetrads, correction blocks, switching and synchronization blocks 1.

Недостаток известного преобразовател состоит в относительно низком быстродействии , св занном с необходимостью двух тактов на один шаг преобразовани , а также в сложности преобразовател , св занной с наличием блоков анализа содержимого тетрады .A disadvantage of the known converter is the relatively low speed associated with the need for two clock cycles per one conversion step, as well as the complexity of the converter associated with the presence of blocks of analysis of the tetrad content.

Наиболее близким к предлагаемому по технической сущности вл етс преобразователь двоичного кода в двоично-дес тичный, содержащий сдвиговый регистр, выполненный в виде п последовательно соединенных тетрад,, где п-число разр дов двоично-дес тичного кода, п блоков коррекции, выходы трех младщих разр дов каждого из которых соединены с информационными входами трех старших разр дов соответствующихThe closest to the proposed technical entity is a binary-to-decimal binary code converter containing a shift register made as n sequentially connected tetrads, where n is the number of bits of the binary-decimal code, n correction blocks, the outputs of three junior the bits of each of which are connected to the information inputs of the three senior bits of the corresponding

тетрад, выход старшего разр да i-ro (i 1 - (п-1) блока коррекции соединен со входом младшего разр да (1-ь1)-ой тетрады , входы каждого блока коррекции соединены с разр дными выходами соответствующей тетрады 2.tetrads, the high-order output of the i-ro (i 1 - (p-1) correction block is connected to the low-level input of the (1st-1) st tetrad, the inputs of each correction block are connected to the discharge outputs of the corresponding tetrad 2.

Недостаток данного преобразовател состоит в относительно большой сложности, св занной с трудностью применени блоков повышенной степени интеграции.The disadvantage of this converter is the relatively large complexity associated with the difficulty of using blocks of a higher degree of integration.

Цель изобретени - упрощение преобразовател .The purpose of the invention is to simplify the converter.

Поставленна цель достигаетс тем, что в преобразователь двоичного кода в двоично-дес тичный , содержащий сдвиговый регистр , выполненный в виде п последовательно соединенных тетрад, где п-число разр дов двоично-дес тичного кода, п блоков коррекции, выходы трех младщих разр дов каждого из которых соединены с информационными входами трех старщих разр дов соответствующих тетрад, выход старщегоThe goal is achieved by converting a binary code into a binary-decimal, containing a shift register, made in the form of n series-connected tetrads, where n is the number of bits of the binary-decimal code, n correction blocks, the outputs of the three lower digits of each of which are connected to the information inputs of the three leading bits of the corresponding tetrads, the output of the senior

Claims

bit of the i-th (ii - (p-1) correction block is connected to the input of the younger digit of the (1 + 1) -th tetrad, the inputs of each correction block are connected to the discharge outputs of the corresponding tetrad, additionally contains two keys for each tetrad and an inverter, and the correction unit is made in the form of a four-bit summatr, the output of the higher bit of which is connected directly to the control input of the first key and through the inverter to the control input of the second key of the corresponding tetrad, the outputs of the keys are connected respectively to the shift input and the input records of the corresponding tetrad, the inputs of all keys are connected to the synchronization input of the converter.The drawing shows a block diagram of the converter.The proposed converter contains tetrad 1, a correction block 2, made in the form of a four-bit totalizer, the first 3 and second 4 keys and an inverter 5. Output the higher bit of the i-ro correction block 2 is associated with the combined inputs 6 and 7 for parallel and serial data input to the lower bit (if. 1) -th tetrad. The high-bit output of the correction unit 2 is also connected to the control inputs of the key 3 and through inverter 5 to the control input of the key 4. The output of the key 3 is connected to the data recording input to the tetrad, and the output of the key 4 is connected to the data shift input in the tetrad. The inputs of the keys are connected to the input 8 of the synchronization of the Converter. The converter works as follows. During each conversion cycle, the number three is added to the contents of tetrad 1 in correction block 2 regardless of the value of the number coming from notebook 1. If the result is less than eight, which is equivalent to the original content of the tetrad being less than five, then the output of the higher bit of the correction unit 2 produces a logical signal "O with which key 3 is locked. This same signal, converted by inverter 5 into logical" 1, opens key 4. As a result, the clock pulse from synchronization input 8 the converter causes data shift in the tetrad, and since the signal from the high bit output of the correction block passes to the inputs 6 and 7 of the next tetrad, and the 6 and 7 inputs of the tetrad under consideration receive a signal from the high bit output of the previous tetrad, and triggers of lower order bits of the considered and next tetrads. If as a result of adding the number three to the contents of the tetrad at the output of the high bit of the correction block, a logical signal "1, that is, the original content of the tetrad is greater than five, then with this signal the clock pulse from the converter input clock 8 is passed through the key 3 to the tetrad, by means of which the offset number from the correction block 2 is written to it with a one-digit shift in the direction of increasing the value, and the new states are written to the lower digits of the considered and following uyuschey notebook. Thus, in the proposed converter, blocks of analysis of the tetrad correction blocks are excluded, which simplifies the converter. At the same time, the operation of the converter is simplified, since for each conversion cycle, depending on the state of only one element of the correction block, either the data shift operation in the tetrad or the writing of corrected information into it is performed. DETAILED DESCRIPTION OF THE INVENTION Binary code to binary-decimal converter containing a shift register made in the form of n series-connected tetrads, where n is the number of bits of a E.E.-decimal code, n correction blocks, the outputs of the three least significant bits of each of which are connected with the information inputs of the three most significant bits of the corresponding tetrads, the output of the most significant bit of the i-ro (il - (p-1) correction block is connected to the input of the lower bit of the (1 + 1) -th tetrad, the inputs of each correction block are connected to the bit ones outputs appropriate the tetrade, characterized in that, in order to simplify the converter, it contains two keys and an inverter for each tetrad, and the correction unit is designed as a four-bit adder, the high-level output of which is connected directly to the control input of the first key and through the inverter with the control input of the second key of the corresponding tetrad, the outputs of the keys are connected respectively to the shift and recording inputs of the corresponding tetrad, the inputs of all the keys are connected to the synchronization input of the converter. Sources of information taken into account in the examination I. US Patent No. 3026034, cl. 235-155, published. 1965.

2. V. Thomas RHVNE Serial Binary to Decimal and Binary Conversion IEEE Trans on Comput. 1970, No. 9, p. 808809, des. 2, 4 (prototype).

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