SU1679479A1 - Faber-schouder signal generator - Google Patents

Abstract

The invention relates to automation and computing and can be used in devices for spectral analysis and signal synthesis. The purpose of the invention is to simplify the generator. The generator contains counter 2, integrators 3, keys 5. By increasing the number of keys, it is possible to eliminate groups 4. 1 sludge.

Description

ABOUT

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The invention relates to automation and computing and can be used in devices for spectral analysis and signal synthesis.

The purpose of the invention is to simplify the generator.

The drawing shows the functional diagram of the generator (t - 3),

The generator contains a clock generator 1, m-bit binary counter 2, integrators 3i-34, rn-1 groups of 4 keys 5, input 6 of a single level, outputs 7-14.

The generator works as follows.

The Faber-Schauder signal p (output 7) is generated by integrator 3i from a unit-level signal (input 6). At the bit outputs of counter 2, a system of functions n, ..., rm Rademacher is formed with a period T 2t of cycles, which with the help of integrators is converted into a system of integral functions Rademacher. The signal taken from the integrator Over (output 8) is the Faber-Schauder p2 signal. The Rademacher integral functions from the outputs of the integrators Zs, 34 are fed to the information inputs of keys 5 in the first (left) columns of the respective groups 4. The operating logic of the keys 5 under the bits of counter 2 (the output of the open key is hardware zero) is similar to the logic of the step decoder , ensures that the output of 9-14 different periods of the period of the corresponding integral Rademacher functions and zero values for

outside these segments, the result is Faber-Schauder signals on

Outputs 9-14 generator.

Claims (1)

Claims of the Faber-Schauder signal generator, comprising a clock generator, a counter, t + 1 integrators (2t-number signals), t-1 groups of keys, the clock generator output connected to the counter input, the input of the first integrator is the input of a unit level generator, 1 -th forward bit output of the counter (I 1, t - from the highest bit) is connected to the input of the (1 + 1) -th integrator, the first direct and inverse discharge outputs of the counter are connected to the control inputs of the first and second keys of the first groups respectively informational in The first and second keys of the first group are connected to the output of the third integrator, the outputs of the first and second integrators, as well as the outputs from the first to the keys of the Jth group (J 1, ch-1) are generator outputs, characterized in that simplification of the generator, control inputs (2k + 1 - + and (- + 2р) -th keys of the k-th group (k 2, t-1; I 1,1 s; p 1,2m) are connected respectively to the 1st pr In my memory and inverse bit outputs of the counter, information inputs (2k + 1 - 2m + 2p-1) -th (2k + 1 - 2 | +1 + keys of the k-th group, excluding, are connected to the output (2k 1 - 21 + p) -th key of the k-th group, information tional inputs (2MI - 3) -th and the (2 - 2) -th k-th key group 5 are connected to the output (k + 2) -ro integrator. 0 five 0 five 0