SU1233153A1 - Device for taking sum - Google Patents

Abstract

The invention relates to the field of computing and can be used to build high-speed arithmetic devices operating in the system of residual classes (SOC) and in the position-residual number system (PIC). The purpose of the invention is to enhance the functionality by generating an overflow signal by the device. The device for adding contains the first and second groups of n adders (n is the number of bases of the SOC), the first and second inputs of which are combined and are the inputs respectively of the first and second operands in the SOC. New in The device is that n multiplexers, a mode switch, an overflow driver, and two position code converters into a SOC code, whose inputs are the inputs of the first and second positional operands, and their outputs are connected to the first and second inputs each of the n matrices of the first group, the outputs of which are connected to the corresponding inputs of the overflow generator and the first inputs of n multiplexers, the second inputs of which are connected to the corresponding the outputs n of the adders of the second group, the outputs of the multiplexers are output by the sum of the device, and their control inputs are combined, connected to the outputs of the overflow driver and the mode switch and are the output of the overflow device f-ly. 2 Il. i (О Сю 00 И-А СП 00

Description

eleven

The invention relates to computing and can be used to build high-speed arithmetic devices operating in the residual class system (SSC) and in the position-residual number system (POS).

The purpose of the invention is to expand the functionality by forming a signal

plump,)

FIG. 1 is a block diagram of the device for addition; in fig. 2 block diagram of the overflow driver

The device contains the first converter of positional code 1 into the code of the residual system, the second converter 2 of the positional code into the code of the system of residual classes, input 3 of the first positional operand input 4 of the second positional operand first group 5 of n accumulators, second group 6 of n adders, sum- torus 7 of the first group of n adders, adder 8 of the second group of n adders, input 9 of the first operand to the SOC, input 10 of the second operand to the SOC, overflow generator 11, n switches 12, device 13 output 13, switch 14 modes, element and 15.

The overflow driver 11 contains n binary decoders 16

code to code 1 of P, (P; - base

 J j

JUICE), the input 17 of the overflow driver, the elements AND 18 on the n inputs, the element OR 19, the output 20 of the overflow driver.

Mode switch 14 is a key with which a zero potential is supplied to the control inputs of the nc switchings 12.

The proposed device can operate in two modes to sum up the numbers represented by the SOC code, and to summarize the numbers represented by the positional (binary) code.

The need to develop such a device is due to the fact that due to the transition in the positional devices to the base of the number system Sj is much higher than the deuce, the speed of calculation quickly increases. The most appropriate (at least at the present time) base value is. This value is known to be called a byte. If

,

Q 5 „

532

within the byte to leave the traditional binary arithmetic, the effect of the transition to S 2 will not be received. If, however, a different coding (for example, a SOC) is used within a byte, which allows the operation to be parallelized across several bases, the effect of moving to a large S increases with increasing S.

The machine word of a modern computer is usually 2 or 4 bytes long. Then the adder of such a computer can be built on the basis of two or four proposed devices. At the same time, each byte of the source data represented by the binary code is converted by means of converters 1 and 2 into an ROC code for p bases Pj such that S i P / 2, where P p P; SOC range. Such a requirement for P is associated with the need to form a transfer signal V (overflow through S) from a younger S-like bit to a higher S-ary bit. Since the bases of the P-SOM are mutually prime numbers, of which only one can be even or multiple degree of two, then it is impossible to choose an S that would satisfy the condition 2 S Р / 2 (where, in the particular case,). Therefore, in the following, we assume that S. The most successful SOK base set for is P 8, P, 5, PO, 13, for which P 520, P / 2 260. Convenience of such bases consists in simplifying converters 1 and 2, since The base of P8 can be taken from its three lower binary bits. Then the transducers 1 and 2 should form only residues at the bases of P 5 and P 13. In general, this simplification is not always possible to achieve, so the drawing is made for a general case. Binary base depth is, m log P, is the nearest large and white. So for the given 0 base set m ha + t + i, 3 + 3 + 4 10 bits.

If transducers 1 and 2 are executed (UB based on PLA 556 series, then for each of them you will need to use three 256x4 bit packages.

The device works as follows.

Mode with uprands in the code JUICE.

0

SS

Switch 14 of the mode delivers (a head potential. Operands represented by a JUICE code according to n grounds in the form A (,, ,,.,. ,,) and a („ft,,.., Р |), А: Р , БР, through the inputs 9 and 10 arrive at the corresponding inputs of the adders 7 and 8 of the first 5 and second 6 groups. On the code of the adders 7 of the first group 5, the value

G - А + В (с, о / + (,, Э, .., D.).

about. ) +

P

, 2,

The output signals of the adders 8 of the second group 6 are not used in this case, since the mode switch 14 zeroes the overflow shaping output and the outputs of the switches 12 are passed to the value C. G. The summation result C, like the initial operands, is represented by residues at the bottom of the JUICE .

Mode with operands in positional (binary code). The mode switch 14 does not supply a zero potential.

Operands presented 1 bit d-

the binary code in the form of a a 1

five

B.2

moreover A S, B S,

50 55

S 2, where S is the base number of the number system. Operands A and B through inputs 3 and 4 are fed to the first 1 and second 2 converters, where they are converted into a JUICE code, each 35 in paracellists, From the outputs of converters 1 and 2, and the operands A and B in the JUICE A code ( Of, S, ...,) and B (jB, E Ph arrive at the first and second inputs of adders 7 and 8 40 of the first 5 and second 6 groups, the outputs of which form the values of G and

50 55

where G

А + В - S - ((,, с ./, о) +

-Kls, i, ... ,, / / - (s, .s, s).

The overflow driver 11 generates the V signal according to the rule (O, if G S

one,

if G S, oh if V 0

then C -

G if V 1.

Since the value of S is a constant, its subtraction can be taken into account when drawing up the tables for which operations are performed in the adders 8 of group 6. These tables are calculated with a shift (by

15

25

20

35 40

five

well - (S) P, for each of the bases of JUICE. So, for the set of foundations considered in the materials of the application, the value is S / O, 1, 9 / -, i.e. 5, on the first base, the correction is equal to O p O, p -1, n -9, s using signal v to the outputs n of switches 2 is transmitted either G or & and the overflow signal is cleared from the output. 10 Thus, the proposed device generates an overflow signal, which allows it to operate in. SOK, PIC and binary operands.

Claims (2)

1. A device for summing, containing the first group of n adders, the first and second inputs of which are the inputs of the first and second operands, respectively, represented in the system of residual classes of the device, characterized in that, in order to expand the functionality by forming the device the overflow signal, the device contains the second group of n adders, n switches, the mode switch and the AND element, the overflow driver and two position code converters into the system code cing classes, first and. the second inputs of the first group of adders are connected respectively to the first and second inputs of the second group of adders, the inputs of the position code converters to the code of the residual classes system are the inputs of the first and second positional operands of the device, respectively, and the outputs are connected respectively to the first and second inputs of each of the first adders the groups whose inputs are connected to the corresponding inputs of the switching generator and the first information inputs of the switches, the second information inputs of which They are connected to the corresponding outputs of the adders of the second group, the outputs of the switches are the output of the sum of the device, and 0 the control inputs of the switches are connected to the overflow output of the device and the output of the AND element, the inputs of which are connected to the output of the overflow driver and the mode switch. 2. A device according to claim 1, characterized in that the overflow driver comprises n descryp binary code raters to code 1 from P, n AND elements, OR element, the output of which is the output of the overflow driver, the binary code decoder inputs to code 1 from P; are the shaper inputs the overflows, the same inputs of the And elements are combined and connected to the outputs of the corresponding binary code decoders in code 1 and P-, the output of the 6 And elements connected to the input of the OR element. Zhgyg Tgp g -N / / 5 FIG. one hedgehog t J