SU1001085A1 - Device for computing complex number modulus - Google Patents

Description

(B) DEVICE FOR CALCULATING THE COMPLEX MODULE NUMBER

one

I

The invention relates to computing.

A device is known for calculating a modulus of a complex number containing registers, adders, switches, shift blocks, elements. NOT, a G11 character analysis block;

The disadvantage of this device is low speed.

The closest to the proposed technical entity is a device for calculating a module of a complex number, which contains registers, adders and switches, when- 5 than the inputs of the first and second registers are connected to the first and second inputs of the device, direct outputs of bits the first register is connected to the group of first inputs of the first totalizer-20 ra, respectively, the output of the first switch is connected to the first input of the second adder. the direct outputs of the first register bits are connected to

the first groups of information inputs of the first and second switches, the second groups of information inputs of which are connected to the direct outputs of the bits of the second register, the inverse outputs of which are connected to the group of second inputs of the first adder, the output of which is connected to the control inputs of the first and second switches, the output of the second switch connected to the second input of the second adder, the output of which is connected to the output of the device 2 J

A disadvantage of the known device is its low speed.

The purpose of the invention is to increase the speed of the device.

The goal is achieved by the fact that a device for calculating a complex number module containing registers, adders and a switch, with the bits of the first and second registers connected to the information inputs of the device, the forward bits of the first register bits are connected to the first group of inputs of the first adder, the inverse outputs of the bits of the second register are connected to the second group of inputs of the first adder, the direct and inverse outputs of the sign bit which are connected to the control input of the switch, the device It also contains the third adder, and the first group of inputs of the second adder is connected to the direct outputs of the first register bits, (n-2) of the upper bits of which are connected to the first group of inputs of the third adder, the second group of inputs of which are connected to the direct outputs of bits the second register, the direct outputs (p-2) of the higher bits of which are connected to the second group of inputs of the second adder, the outputs of the bits of the second and third adders are connected to the first and second group of information inputs of the switch, respectively, d is connected to the output device. The drawing shows a block diagram of the device. The device contains the first register 1, the second register 2, the first adder 3, the second adder, the third adder 5, the switch 6. The device operates as follows. At the initial moment of time, the first register 1 and the second register 2 are entered into the n-bit mantissas of the direct codes of the real and imaginary components of the complex number, respectively. From the output of the first register 1, the direct code of the real component goes to the first inputs of the first 3 and second adder, and the n-2 most significant bits of this code go to the first input of the third adder 5. From the output of the second register 2, the inverse code of the imaginary component arrives at the second input of the first adder 3, the direct code goes to the second input of the third adder 5 a n-2 most significant bits to the second input of the second IT code of the adder k. The signal from the output of the sign bit of the adder 3 is fed to the control input of switch 6, the first information inputs of which are fed from the output of the second adder k, the result of adding the code of the real component to the imaginary, shifted two bits to the side of the lower bits. The second information inputs of the switch 6 come from the output of the third adder 5, the result of adding the imaginary-component code to the real one, which is shifted by two bits to the side of the lower bits. With an appropriate control signal applied to the switch, its output results in the addition of a larger component of a complex number with a smaller component shifted two bits in the direction of the least significant numbers. Row Switch 6 is a set of n elements 2 AND-OR, the inputs of each element are respectively signals from the outputs of the second and third adders 4 and 5 and. two control signals, the direct and inverse signals of the sign bit. At the output of the switch 6, depending on the control signals, a result is obtained that is taken from the output of the second or third adders k or 5 The device allows the calculation of the modulus of the complex number with increasing speed as compared with the prototype. The calculation time in the proposed device is shorter compared to the prototype for the delay of the adder (with an insignificant change in the equipment costs, instead of one switch, a third adder is entered). The implementation of a device for computing a complex number module is associated with the development of digital signal processing in spectral analysis problems and is a new promising area of computing technology. The device, in comparison with the prototype, allows to increase the speed of calculation of the modulus of a complex number. The delay introduced by the basic device, + TC, where 17 is the delay of the adder; switch latency. The delay introduced by the device ;; Cc.t K + Cc taking into account that ,,. The gain in speed without significant changes in equipment costs is T - p T (., Relative gain - f TdG. With Te

Claims (2)

Claims An apparatus for calculating a complex number module comprising registers, adders and a switch, wherein the inputs of the first and second registers of the registers are connected to the information inputs of the device, the direct outputs of the first register bits are connected to the first group of inputs of the first total. The inverse outputs of the bits of the second register are connected to the second group of inputs, the first adder, and the direct and inverse outputs of the sign bit. which is connected to the control input of the switch, which differs from J} in that, in order to increase the speed of the device, a third adder is inserted into it, and the first group of inputs of the second adder is connected to the forward outputs of bits 20 the first register (Vi-2) of which high bits is connected to the first group of inputs of the third adder, the second group of inputs of which is connected to the direct outputs of the bits of the second register; the direct outputs (-I-2) of the high bits of which are connected) the second group of inputs of the second adder, the outputs of the bits of the second and third adders connected to the first and second group of information inputs, switch, respectively, the output of which is connected to the output device. Information sources, . taken into account during the examination 1. USSR Copyright Certificate No. 623202, cl. G 06 F 7/38, 1976. 2. USSR author's certificate in application number 2977566 / 18-2, cl. G 06F7 / 38, 1978 (prototype). 1001085 five