SU1647556A1 - Device for summing number bulks - Google Patents

Abstract

The invention relates to computing and can be used in high-performance digital information processing devices. The aim of the invention is to expand the field of application by performing the summation of numbers with different signs. The goal is achieved by introducing a one-bit multi-input adder, a permanent storage unit and a parallel adder, as well as new connections into the device containing the memory block, the adder for group addition of numbers and the output register. The device can summarize the numbers in the additional and reverse code. The summation of numbers with different signs is accomplished by adding a correction code, read from a permanent storage unit at the address that is the code of the number of negative numbers, to the sum of the mantissa numbers. 2 Il. (L

Description

The invention relates to computing technology and can be used in high-performance digital information processing devices.

The aim of the invention is to expand the field of application by performing the summation of numbers with different signs.

FIG. 1 shows a block diagram of the device; in fig. 2 shows a variant of constructing a block diagram of a device for summing an array of numbers in the return code.

A device for summing an array of numbers contains a storage unit 1, an adder 2 for group addition of numbers, a one-bit multi-input adder 3, a permanent storage unit 4, a parallel adder 5, an output register 6 and a synchronization input 7. The storage unit 1 is a group of N n-bit registers or memory cells with the possibility of simultaneous access to all registers (cells) simultaneously and can be executed in the form of an associative memory device. The adder 3 is designed to determine the number of units in the signed slice of the terms.

The device performs summation of N n-bit binary numbers, represented as (n − 1) - bit d-.

4 SL SP

F

one mantissa and one sign of the distribution.

The basis of the device is the following method.

Let the array components be represented as:

n-n-4 o H „-K + q,;, K + ... + q, n.K;

q (-KMH + qz .... + qn K °; 10 qN / Kh + qNi Kh 1 + -. + qNn-K0,

where K is the base of the number system; q -t is a coefficient that takes the corresponding value at 15 numbers represented in the number system with base K. For the binary system, we represent the same array of terms in the binary bit system of the result-20 tat, i.e. of n + jlog nf, and the sign bit is transferred to the leftmost position, then:

q Mleog C-i gn1 gmg-g 25

1 i

  2 5 p g q2, 2nVo9 NC- + qn. +

 : $ srg.no + .iuJtffcit-V

qN, + qNZ

+ - + ZDbo mS 2 °

Since the size of the initial terms is n, all negative numbers, when represented in the reverse or additional codes of the n + logtNLB position, start from 2П to 2n4e ° N z) have units that we call fictitious, since they are absent in the original addend codes. Let the negative numbers and the array be K. Then, to get the correct result of adding the different numbers, it is necessary to sum the mantis

, ql2 2n 2 + q V2n 3 + ... + qftl-2 °;

, 2n-4 l2J.2t1- + ... Ul

"

Yam2-2 g-N1y} 2I e + ...- K1Mp-2 of the primary array add the number

(2g | eo si fa. "C-

to j

 sign bit)

When obtaining the sum of an array of variable components, it is obvious that the form of the representation of the terms should be taken into account.

Thus, if the addends are represented in an additional code, all carry units that exceed the n + Jlog NL size are ignored.

If the numbers are in the reverse code, all units of carry that are larger than the n + Jlog size NЈ, cyclically, in accordance with their positions, add up to the lower digits of the amount received.

Transform the value of pk, can be obtained as follows

P, .K. (23e CrtJfc: ... rt0)

in this case, K generally runs from 1 to N. Since any P number is a multiple of 2, to obtain the final sum, you need to know

numbers

 fcjfcNC-i о (2 +2 3 + ... + 2),

which can be stored in memory. In this case, for reading the necessary number from the memory, it is necessary to know the number of units in the signed slice (i.e., the number of negative terms), which is the address of the number Pn.

To obtain the final sum, it is necessary to sum the sum of the mantissas of the initial terms with the number Pk shifted relative to this sum by n-1 bit to the left.

The device works as follows.

The bit sections of the terms are accessed on the corresponding inputs of the adder 2, and the bit section of the sign bit is on the input of the adder 3, which forms the code for the number of units in this section, i.e. the number of negative numbers in the array. This code is (2-3log2Nf) bit, while if the terms are presented in an additional Code, then the bits of the persistent storage unit 4 Glog2NL + 1) -ro by (2 "3log., N) -u contain zeros, those. these bits are not used. When summing numbers in the reverse code, the parallel adder 5 must contain a cyclic transfer circuit (FIG. 2). The result of the summation is entered in register 6 along the trailing edge of the synchronization pulse on input 7.

Consider for example the summation of numbers in the additional code. The amount of mantis is determined in the following way: +5

+6

+ 7 -S

-z

-one

Since the result size is seven, the output of the adder 2 is 0.100001. Since the array contains three negative numbers, a 011 code will be generated at the output of the adder 3, i.e. 3 in binary code. This code is the address for reading P3, which is the sum of the dummy units and characters from block 1, i.e. number will be read. End- ((The sum of the array is defined as; 0.100001

1.101

.0.001001

+9

Claims (1)

overflow unit is ignored. Invention Formula A device for summing an isel array containing a storage unit, an adder for a group of complex numbers and an output register, and the outputs of groups of like bits of the components of the storage block are ;  6 foams with corresponding inputs of the adder for group addition of numbers, characterized in that, in order to expand the field of application by implementing the summation of numbers with different signs, the device additionally contains a one-bit multi-input adder, a constant block and a parallel adder, and the outputs are signed the bits of the terms of the storage unit are connected to the inputs of a one-bit multi-input adder, the output of which-15 dew is connected to the address input of the permanent storage unit, the bit The outputs of the adder for group addition of numbers are connected to the corresponding bits of the first input of the parallel adder, the bits of the second input of which from the first to Jlog2N -ft are connected to the output bits of the permanent storage unit from pog-H) to (2 -11or, gn), and 25 bits from the nth to (n + logll $ -) -Pi are connected to the output bits of the constant storage unit, respectively, from the first to JlogjN -ft, where N is the number of terms, an is the bit size of the items, the output of the parallel adder is connected with the information input of the output register, the output of which is the output of the device result, the synchronization input is cleared. A passing block is connected to the synchronization input of the output register and connected to the synchronization input of the device; free bits of the inputs of the parallel adder are connected to the zero potential bus of the device. GC S J -h ./ & .Ј