SU1608644A1 - Device for processing series code of golden proportion - Google Patents

Abstract

The invention relates to computing and can be used to build specialized computing devices. The purpose of the invention is to expand the scope of application by separating the fractional part of the code. The device contains a counting trigger 1, shift registers 2, 3, elements AND 4, 5, element OR 6, triggers 7, 8, sequential subtractor 9, 10 number input, mode setting input 11, clock input 12, initial setting input 13 and output 14. 1 Il., 2 tab.

Description

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FIELD OF THE INVENTION This technique can also be used with trigonometric, exponential, and other computation devices. functions for separating the fractional part of the sequential code of the number represented in the golden ratio code

The aim of the invention is to expand the scope by separating the fractional part of the code.

The drawing shows a diagram of a device for processing a serial code of the golden ratio.

The device contains a counting trigger 1, the first 2 and second 3 shift registers, the first 4 and second 5 elements AND, the element OR 6, the first 7 and second 8 triggers, a serial reader 9, the input 10 the device number, the input 11 of the device mode setting , clock input 12 of the device, input 13. the initial installation of the device, output 14 of the device.

As a subtractor 9, a serial adder of codes with irrational bases may be applied. To perform a subtraction operation, a positive sign was given to the input of the sign of the first term, and a negative sign was given to the input of the sign of the second term.

The essence and the physical possibility of separating the fractional part of the sequential code of a number represented in the code of the golden ratio are as follows.

In the number system of the golden proportion, an arbitrary number is depicted as the sum m-t,

Am, ii a, s,

, -p where (x is the base of the number system,

. + -, shu. t oi 1,618. ..,

m is the number of bits with positive exponents; n is the number of bits with negative exponents; , is a binary i-digit code.

Denote the integer part of the number I (Am, .n), and the fractional part of F (Am, n), then

I (Am, n) Am:, n-F (Am, n). In turn, F (Am, n) F (F (Am) + F (An)),

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Where

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In the redundant numbering system of the golden proportion, with non-minimal forms, codes with negative exponents σ can also represent numbers greater than one. To isolate from such a code.,. the fractional part, it is necessary to reduce it to the minimum form, discarding the overflow unit.

Thus, the singularity of separating the whole and fractional parts in the number system of the golden ratio is in the calculation of F (Am), i.e. the fractional part of the number represented in the bits of the s. positive indicators of the degree-ivi. Next, a device for determining the fractional part of the sequential code of the number represented in the bits with positive powers is considered.

With positive exponents, to determine the fractional part, it is necessary to determine how much the random weight of the discharge differs from the whole number.

The relationship of the degrees of the golden proportion with Luke numbers:

fed + o for even i; ; . (X - (X is FOR odd L; that is, (i) + (- i) V-;

However, L (i) is an integer. Then Ani Xa; -L (i) + a (, - (-1) +

m-i:. I. a; (- l) V-;

i (In this expression, the last member

is the fractional part of F (Am).

To determine the fractional part, it is necessary to add up, taking into account the signs, the codes formed by each bit a; (-) Ы, т, е, practically from one code represented in the minimal form to subtract another. In this case, taking into account that the bits with even numbers aMii code are located one bit from each other, also bits with odd numbers are located one bit from each other, total sums a; o for even or odd i does not exceed one. However, depending on the values of the bits of the source code Am, the fractional part of F (Am) can be either positive or negative. In order to obtain a positive value, F (Am) requires, from a unit, a module, a negative number.

The device works as follows | zomo

A pulse arrives at the input 13 of the initial setup, which sets the shift registers 2 and 3 and the triggers 7 and 8 to the zero state, and the trigger 1 to the zero state, if m is even, and to one state, if m is odd. Then, a single potential arrives at input 11, which will allow the passage of information through elements 4 and 5, set the shift Bbje registers 2 and 3 into the shift mode

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zero state. The input 12 receives clock pulses. Synchronously, the leading edge of each clock frequency at input 10 is received, starting from the highest one, the bits of the successive code of the number represented by the golden ratio code, and the trigger changes its state to the opposite

In the shift register 2, the values of the bits with odd stems of the base number system are written, in the shift register the 3rd even ones. At the same time during the recording

information B register 2 in the register 1 is written zero bit, on the contrary. Trigger 7 sets periodically to O, then I, depending on the values of bits B5 of one code. At the moment of arrival, the input of a sequential code of a digit with a weight (Y, at the input 1 1 sets zero potential.

this prohibits the passage of information through elements 4 and 5, the shift shift registers 2 and 3 are translated. In the right shift mode (spinning information), Trigger 7 will remain in one state, if the last number in the code was one with an even degree of discharge, and in the zero state with an odd exponent, this achieves the introduction of a unit to subtract when receiving from π1 valuable F (Am).

From the output of the shift pegister 2 infs: | Rmaci a sequential code through the trigger 7 to the input of a moderate sequential subtractor 9. From the output of the shift register 3

Shs

information in a sequential code is received via trigger 8 at the input you-. of the readable consecutive subtractor 9 o At the output of the subtractor 9, as a result of the subtraction of consecutive codes, a sequential code of the fractional part F (Am) is formed,

. Let us consider in more detail the operation of the device when allocating the fractional part of the sequential code of the number 278, 6362, represented by the golden proportion code in the form:

oi VV ot Vo "VV o o

five

 1101100101 Here - the odd. At the input 13 of the initial installation receives a pulse that sets the registers and 3, the triggers 7 and 8 in

0 the zero state and the trigger 1 are in the single state. Then, a single potential arrives at the input P, and the highest bit (one) arrives at the input 10 with a weight about {synchronously with the front clock edge. On the leading edge of the first clock pulse, trigger 1 is set to O. The shift registers 2 and 3 are set to the left shift mode. At the output of element H 4, a single signal is set, which translates trigger 7 into one state. When the leading edge of the next clock pulse arrives, 1 is written to register 3, 0 is written to register 2, O is set to 1 at input 10. A second bit is input to input 10 (1) with a weight of:. At the output of the element 5, a single signal is formed which sets the trigger 7 to the zero state. With the arrival of the leading edge of the next clock pulse, the register 2 is pushed in - T, the register 3 is pushed in, the trigger 1 is set to the zero state. Input 10 receives the next bit (1) with a weight x: ®. At the output of the AND 4 element, a single signal is generated, which sets the trigger 7 to 1.

0 With the arrival of the leading edge of the next clock pulse, register 3 is pushed 1, register 2 is pushed O, trigger 1 is set to 1. Input 10 receives the next bit (O) with a load (, At the outputs of elements I.4 and 5, the potentials are zero , trigger 7 of its state does not change with the arrival of the leading edge of the next clock pulse in the registers

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2 and 3 zeros are pushed in, trigger I is set to zero. The next bit (unit) with the weight oi of the sequential code arrives at input 10

Further work happens in a similar way. When entering input 10

ten

Operators with a weight of about trigger 7 is set to 1. and the zero value of the bit with the weight of the state of trigger 7 does not change. With the arrival at the input of the 10 bit with the weight od, the zero potential arrives at the input P and prohibits the passage of information through the elements 4 and 5 o. By this time the trigger 7 is in single state

eight

and in registers 2 and 3 recorded codes are given in table. one ,

I Zero potential at input-11 translates shift registers 2 and 3 into right-shift mode. In this case, the information from the registers is advanced, starting with the bits with the weight Ы, and therefore, the order of weights of the bits changes the sign of the unit in trigger 7 has oi о. Thus, at the inputs

weight

consecutive subtractor 9 receives the codes given in the scoreboard 2 „

At output 14, as a result of subtraction, a code is generated.

oi- 1

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0.6362, which is the fractional part of .278, 6362.

Claims (1)

Invention Formula 25 A device for processing the serial code of the golden ratio, containing the first and second shift registers, the first and second triggers, the OR element, and the serial subtractor, the output of the last subtractor being the output of the device, the clock input of which is connected to the clock inputs of the first and second the shift registers and the serial subtractor, with the resolution inputs of the recording of the first and second triggers, the input of the initial installation of the device is connected to the inputs of the installation in the first and second shift register in and second trigger, about t l and 40 often in order to expand the application area by separating the fractional part of the code, it contains a counting trigger, the first and second elements are AND, the device number input is connected to the first inputs of the first and second elements AND, the mode setting input is connected to st | - 0 about O / - o ( ABOUT -8 -9 1 - about( ABOUT one five 0 15 the second inputs of the first and second elements And, with the inputs of the direction of the shift of the first and second shift registers and with the installation input in O of the serial subtractor, the input of the initial installation of the device is connected to the installation input of the counting trigger and the first input of the element OR, the output of which is connected to the installation input in P the first trigger, the output of which is connected to the input of the decremented serial subtractor, the input of which is subtracted is connected to the output of the second trigger, the information input of which is connected to the output The second shift register, the information input of which is connected to the installation input to the first trigger and with the output of the first element I, the clock input of the device is connected to the information input of the counting trigger, the inverse and direct outputs of which are connected respectively to the third inputs of the first and second elements I, the output of the last connected to the second input of the OR element and to the information input of the first shift register, the output of which is connected to the information input of the first trigger Weight is yes oi -0 - ( Input A (reduced) 1 About 0001 About About About 1 About Input B (subtracted) 00100010101 1608644 10 Table2 -z / - - , -b, -t 04- od- oi-