SU1654838A1 - Device for calculating ordinal statistics - Google Patents

Abstract

The invention relates to computing and can be used in high-speed digital signal processing systems, in particular for median filtering of images in order to suppress impulse noise. The purpose of the invention is to increase the speed. The device contains a group of registers 1, adder 2, comparator 3, groups of flip-flops 4, blocks 5 of determining the order of the random statistics.j Il.

Description

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The invention relates to computing and can be used in high-speed digital signal processing systems, in particular for median filtering of images in order to suppress impulse noise.

The purpose of the invention is to increase speed.

The drawing shows a functional diagram of the device.

The device contains a group of 1 registers, an adder 2, a comparator 3, a group of flip-flops 4, a block 5 for determining the bit of the order statistics, an input 6 for setting the comparison threshold and an output 7.

Each block 5 for determining the order statistics contains the elements EXCLUSIVE OR 8, switches 9, registers 10, adder 11 and comparator 12.

The device works as follows.

The input of device 6 receives the threshold value of comparison T p-g + 1, where n is the number of numbers in the neighborhood, an odd number, and r is the number of the order statistics (for example, when calculating the median T

n + 1 t-, when calculating the maximum

T 1, and when calculating the minimum T n).

With the help of adders 2 and 11 in blocks 5, the sum of the higher bits in registers 1 and 10 is determined. This sum is compared with the help of comparators 3 and 12 with the threshold value T, i.e. adders 2 and 11 and comparators 3 and 12 implement the following function

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1, if a. T,

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Oh otherwise

where a. - the value of the high bit of the corresponding registers 1 and 10 (p T, t) o When p 1, the high bits of registers 1 are analyzed, with p 2 - the high bits (modified second bits of the original numbers) of registers 10 of block 5.1, with q 3 , m - the highest bits of registers 10 of block 5.2-5t-1.

Using the elements EXCLUSIVE OR 8 and switches 9 in block 5, the corresponding numbers are converted so that the registers 10 of block 5 record the values of the numbers without changing (the lower digits of the numbers, starting with (K + 1) -th bit (K 1, t -1), where K is the number of the bit being analyzed), if the value of the bits being analyzed is a. coincides with the value of the K-th bit of the order statistics determined using adder 2

(11) and comparator 3 (12). In this case, at the output of the EXCLUSIVE OR 8 element, a zero level is formed, which allows the lower digits of the corresponding numbers to pass through the switches 9.

If a member of the EXCLUSIVE OR 8 element does not match, a high level is formed, which allows passing the corresponding most senior (at the previous analysis level) bit through the switches 9.

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Claims (1)

Invention Formula A device for calculating order statistics, containing groups of n (n is the sample size) of registers and the first block for determining the order of the order statistics, containing n switches and n EXCLUSIVE OR elements, the first input of the 1st (i 1, ... , n) the EXCLUSIVE OR element and the information input of the 1st switch of the first block of determining the order statistics are connected to the high bit of the 1st register of the group, characterized in that, in order to increase speed, an adder, comparator, trigger, t-1 (t - bit days elements of a sample of trigger groups, tp-2 blocks of determining the order of the bit statistics identical to the first one, and in each block of determining the bit of the order of the statistics are entered registers, adder and comparator, and in each block of determining the bit of the order statistics, the output of the 1st switch is connected to the information input of the i-ro register, the high-order output of the 1st register is connected to the i-th input of the adder, the output of which is connected to the first input of the comparator, the group of low-order bits of the 1st register groups connected to the group of information inputs of the 1st switch of the first block of determining the discharge order statistics, the output of the higher bit The i-th register of the group is connected to the 1st input of the adder, the output of which is connected to the first input of the comparator, the output of the comparator is connected to the second inputs of the EXCLUSIVE OR elements of the first block for determining the bit order statistics and the input of the first trigger of the first group, the group of low-order outputs Dates of the 1st register of the jth (j 1, ..., ha-2) block for determining the bit of the order statistics are connected to the group of information inputs of the 1st adder (jH) of the block for determining the bits of the order statistics, output the older bit of the 1st register j-ro the block of determining the size of the order statistics is connected to the information input of the 1st switch and the first input of the 1st element EXCLUSIVE OR j + 1) of the block determining the size of the order statistics, the output of the comparator j-ro statistics connected to the second 0 0 the inputs of the EXCLUSIVE OR (j + 1) - block for determining the bit of order statistics and information input of the first trigger (j + 1) - and group, the second inputs of the comparators of blocks for determining the bit of order statistics and the second input of the comparator are connected to the input of the threshold setting device comparison, the direct output of the 1st (1 1, ..., tK) trigger of the Kth (K1, ..., tp-1) group is connected to the information input of the (1 + 1) -th trigger . the jth group's gerard, the last output of the last K-group's trigger is the output of the corresponding bit of the device's stat statistics, the output of the comparator of the (th-1) th block of the order of the statistical bits of the trigger is connected to the trigger information input, direct the output of which is the output of the m-th bit of the order statistics of the device. 25