SU792251A1

SU792251A1 - Apparatus for parallel shifting of binary numbers

Info

Publication number: SU792251A1
Application number: SU782702956A
Authority: SU
Inventors: Юрий Антонович Кипецкий; Богдан Иванович Смертыга; Владимир Моисеевич Тафель; Анатолий Филиппович Теслюк
Original assignee: Предприятие П/Я В-8751
Priority date: 1978-12-27
Filing date: 1978-12-27
Publication date: 1980-12-30

Description

1one

Изобретение относитс к вычислительной технике и может быть исполь зовано в ЦВМ дл ускоренного выполнени арифметических и логических операций.The invention relates to computing and can be used in a digital computer for accelerated execution of arithmetic and logical operations.

Известны схемы реверсивных сдвигающих регистров 1J .Known schemes reverse shift registers 1J.

Недостатком таких регистров сдвига вл е тс низкое быстродействие при организации сдвига информации на несколько разр дов, который осуществл етс как последовательность сдвигов на один разр д.The disadvantage of such shift registers is the low speed in organizing information shifts for several bits, which is implemented as a sequence of shifts per bit.

Известна также схема ускоренного сдвига информации на заданное число разр дов 2. В этой схеме имеютс самосто тельные цепи сдвига на 2 разр дов, где п 1, 2, ...,0°. Сдвиг на любое число разр дов комбинируетс из указанных элементарных сдвигов.Also known is the scheme of accelerated shift of information by a given number of bits 2. In this scheme there are independent shift chains of 2 bits, where n is 1, 2, ..., 0 °. The shift by any number of bits is combined from the indicated elementary shifts.

Недостатком такой схемы вл етс недостаточно высокое быстродействие, так как количество тактов равно числу разр дов в двоичном коде задан-ного количества сдвигов.The disadvantage of this circuit is not high enough performance, since the number of clock cycles is equal to the number of bits in the binary code of a given number of shifts.

Наиболее близким к изобретениюClosest to the invention

вл етс расшир емое устройство дл is an expandable device for

параллельного сдвига двоичных чиселparallel shift of binary numbers

З, содержащее т-разр дный регистрH containing t-bit register

...выходы которого соединены с первыми... whose outputs are connected to the first

входами элементов И, расположенных в узлах кососимметричной матрицыумножени , вторые входыэлементов И подключены к выходам дешифратора кода сдвига, третьи входы элементов И подключены к шинам сигналов левого сдвига или правого сдвига, а выходы элементов И поразр дно подключены к соответствующим входам группы the inputs of the elements And located in the nodes of the skew-symmetric matrix multiplication, the second inputs of the elements AND are connected to the outputs of the decoder of the shift code, the third inputs of the elements AND are connected to the buses of the left-shift or right-shift signals, and the outputs of the elements AND are connected to the corresponding inputs of the group

10 элементов ИЛИ, выходы которой соответствуют разр дам двоичного числа и вл ютс выходными шинами устройства. С выхода дешифратора кода сдви1а унитарный код сдвига построчно поступает на входы элементов И кососиммет15 ричной матрицы умножени . На другие входы элементов И поступают код тразр дного двоичного числа и сигналы левого сдвига или правого сдвига. The 10 OR elements, the outputs of which correspond to the bits of the binary number and are the output buses of the device. From the output of the decoder of the shift code, the unitary shift code is line by line fed to the inputs of the elements And the skew-symmetric multiplication matrix. The other inputs of the elements And receive the code of the binary binary number and the signals of the left shift or right shift.

20 На выходе элементов И формируетс результат умножении ш-разр днрго двоичного числа на 2, где п - указатель числа сдвигов. Выходные шины дешифратора кода сдвига, соответ25 ствующие сдвигу на п разр дов вправо, такуке соответствуют сдвигу на т-п-1 разр дов влево,кроме случа сдвига на О разр дов.20 The output of the elements And is the result of multiplying the w-bit of a double-digit binary number by 2, where n is the index of the number of shifts. The output buses of the decoder of the shift code, corresponding to a shift by n bits to the right, also correspond to a shift by mn-1 bits to the left, except for the case of a shift to O bits.

Недостатком устройства-прототипа вл етс его сложность, св занна сThe disadvantage of the prototype device is its complexity associated with

Claims

30 the need to flash the elements of an skew-symmetric matrix in four coordinates. The aim of the invention is to simplify the device. The goal is achieved by the fact that a device for parallel 1-shift binary numbers, containing a t-bit register, a decoder of the shift bias, a matrix of elements AND, a group of elements OR, and the inputs t-times a regular register connected to the input buses of the device, and the outputs with the first inputs of the corresponding elements AND each row of the matrix, the second inputs of the elements AND each row of the matrix are connected to the corresponding outputs of the shift code decoder, the first group of inputs of the shift code decoder is connected to the input buses of the shift code the device, and the second group of inputs to the control buses of the right-shift and left-shift signals, additionally contains m 2 AND-OR elements, the first and second control inputs of which are connected respectively to the control buses of the left-shift and right-shift signals, and the outputs with the output tires of the device, the output of each j-ro element and the i-th row of the matrix (i 1, ..., m; j 1m), except for the first element AND the first row and (N-th element AND the t-th row, connected , with the input of the (i + j - 2) -th element of the OR group, the first information input of the first element 2 AND-OR with the output of the first element AND the first row of the matrix, the first information inputs of each k-ro element 2 are AND-OR (k 2, ..., mj are connected to the output of the (k - 1) -th element of the OR group, the second information input of each 1 of item 2 I-ILY (1 G,. . . , tn - 1) is connected to the output of (t - f 1 - 2) -th element of the OR group, the second information input of the 2-nd element 2 AND-OR is connected to the output of the t-th element And the t-th row of the matrix The devices are shown in the drawings (i. The device for parallel shifting of binary numbers contains a t-bit register 1, a shift code decoder 2-, elements AND 3-18 of an obliquely symmetric matrix, a group of elements OR 19-23, elements 2 K-OR 2427 The control busbars of the signals for the right shift 28 and the left shift 29, the buses of the shift code 30, the input 31 and the output 32 buses of the device. for case m 4. The inputs of register 1 are connected to the input buses 31 of the device, the inputs of the decoder of the shift code 2 are connected to the buses 30 of the shift code and to the control shings of the signals of the right shift 28 and left shift 29. The outputs of register 1 are connected to the first inputs of the elements And 3-18 skew-symmetric matrix on the corresponding oblique columns. The second inputs of the elements And 3-18 skew-symmetric matrix are connected in rows to the corresponding outputs of the shift code decoder. The outputs of the elements And 4-17 in vertical columns are connected to the inputs (2m-3) of the elements OR 19-23. The output of the AND 18 skew-symmetric matrix and the outputs (t - 1) of the elements OR 21-23 are connected to the information inputs of the elements 2 AND-OR 24-27. The outputs (t - 1) of elements OR 19-21 and the output of element AND 3 of an skew-symmetric matrix are connected to other information inputs of elements

2. AND-OR 24-27. The first and second control inputs of the elements 2 AND-OR 24-27 are connected to the control buses of the signals of the left shift 29 and the right shift 28, respectively. The outputs of the elements 2 AND-OR 24-27 are connected to the output buses 32 of the device. The device as follows. The information to be shifted is entered into register 1, from the outputs of which the number goes to the first inputs of the AND 3-18 elements. At one of the outputs of the shift code decoder 2, there is a resolution signal arriving at the selected row of the matrix and corresponding to the code and direction of the shift. From the outputs of the AND 3-18 elements of the selected matrix row, the result of shifting the initial number through the elements OR 19-23 and the elements 2 AND-OR 24-27 enters the output buses 32 of the device. When shifting to the left at the outputs of the decoder of the shift code 2, the resolution signals corresponding to the incremental shift code n (from O to m - 1) are placed in order of increasing (from top to bottom). When shifting to the right at the outputs of the decoder of the shift code 2, the resolution signals corresponding to the incremental shift code n are placed in decreasing order (bottom-up). The final selection of the shift result depending on the shift direction is performed by element 2 AND-OR 24-27. The technical and economic effect is achieved by increasing the manufacturability of the device by reducing the number of firmware coordinates of the skew-symmetric matrix to three and reducing hardware costs (by the criterion of the number of equivalent inputs). Reduced hardware costs with m. -8 is 10% not increasing m asymptotically tends to 25%. Apparatus of the Invention A device for parallel shifting of binary numbers containing t times