SU1137463A1 - Multiplication device - Google Patents

Abstract

A DEVICE FOR MULTIPLICATION, containing multiplier and multiplier registers, AND matrix of elements, OR group of elements, accumulating sumator and low-order allocation unit, with the output of multiplicative register bits connected to the first inputs of corresponding AND columns of the matrix, output j-ro ele. And the i-th row of the matrix- (t 1,. ,,,, ..., ri; n is the size of the factors), except for the first element And the first row of the matrix and the n-th element And the n-th row of the matrix, is connected to the input of the (t + j -2) -th element OR group, distinguishing it so that, in order to increase speed, two buffer registers and a control unit containing a counter, two AND elements and an OR element, a block are entered into the device the selection of the low-order bit contains n, the substitutions of I, and the wrap-up adder is designed as an adder with memory remembrances, with the inputs of the k-ro element AND block you The junior; your bit (1., ..., k-1) is connected to the direct output f1 + n-ro register multiplier and inverse outputs of all previous bits of the multiplier register, the inputs of the nth element And the allocation unit the low-order bit is connected to the inverse outputs of all bits of the register of the multiplier, the direct output of the first bit of which is connected to the information input of the first bit of the first buffer register, the output of the k-ro element AND the allocation block of the low-order bit is connected to the information input (k + l ) -ro bit of the first buffer register, exit For each digit of which is connected to the second inputs of the AND elements of the corresponding matrix row, the output of the first element AND the first row of the matrix is connected to the information input of the first bit of the second buffer register, the output of the p-th OR element of the group (B, ..., 2n -3j is connected to the information input (K + 1) of the second buffer register, information Iso input

Description

the adder and the multiplier register, the zero reset inputs of which are connected to the information inputs of the corresponding bits of the first buffer register, the output of the first element AND of the control unit is connected to the counter input of the control unit, the direct output of the first and the inverse output of the second bit of which are connected

with the inputs of the element 1-SHI, the direct output of the second discharge and the output of the overflow of the second discharge of the counter of the control unit are connected respectively to the control input of the end-to-end transfer of the accumulating adder and the output of the end indication. multiply device operations.

The invention relates to computing and can be used in the development of high-speed multiply devices of asynchronous type.

A device for multiplying is known, containing registers of multiplicable and multiplier, accumulating adder, matrix of elements AND, two groups of elements OR, two groups of elements AND and O group of elements of delay S3.

The disadvantage of the known device is the low speed.

The closest in technical essence to the invention is a device for multiplying, containing registers of multiplicable and multiplier, matrix of elements AND, group of elements OR, group of elements AND, accumulating adder and block of allocation of 20-digit bits, and outputs of register of multiplicable connected to the first inputs of the elements And the corresponding columns of the matrix, the output of the j-ro element And -th row of the matrix 25 il, ..., h; j l, ..., n; n is the width of the factors U except the first element AND the first row of the matrix and the n-th element AND, the n-th row of the matrix are connected to the input of the (i + j-2) -rd 30 elements OR groups, the outputs of the elements OR groups are connected respectively to the inputs of the discharge Dows from the 2nd to (2n - 2) -and accumulating adder, the inputs of the G-th and (1) -th bits of which are connected respectively to the outputs of the first element And the first row of the matrix and the p-th element And the n-th row of the matrix , the inputs of the block of the allocation of the junior bit are connected to the inverse outputs of the corresponding bits of the register Itel,.

and the outputs are connected to the first inputs of the corresponding elements AND group 1, the second inputs of which are connected to the direct outputs of the corresponding register bits, multiplier, and the third inputs are combined and connected to the synchronization inputs of the multiplier and accumulating adder register and the synchronization input of the device, the outputs of elements AND group connected to the second inputs of the elements And of the corresponding row of the matrix and with the inputs of zeroing the corresponding bits of the register multiplier 2.

A disadvantage of the known device is the relatively low speed of operation caused by the large duration of its operation cycle (the duration of a cycle is determined by the time of passing information through the group of elements AND, the matrix of elements AND, the group of elements OR, and the time of summation in the accumulator with end-to-end transfer).

The purpose of the invention is to increase the speed of the device by shortening the cycle time.

The goal is achieved by the fact that, in a multiplying device, containing a multiplier and multiplier registers, a matrix of AND elements, a group of OR elements, a accumulating adder and a low-order allocation unit, the outputs of the multiplicable register bits are connected to the first inputs of AND elements of the corresponding columns of the matrix, the output j-th element And the i-th row of the matrix (il ,, .., n; j 1, ...,; n is the size of the factors), except for the first element AND of the first row of the matrix and the i-th element And the row of the matrix, connected to the input of the -2) -th element of the OR group, entered two buffer registers and a control unit containing a counter, two AND elements and an OR element, a low-order selection block contains "AND elements, and the accumulating adder is designed as a cum with transfer memory, while the elements of the low-resolution IED cell bit (k 1, ..., p-1) is connected to the direct output of the (1 + 1) th register bit of the multiplier and inverse outputs of all previous bits of the register of the multiplier, inputs of the i-th element And the block of the lower bit yes connected to inverse outputs of all bits of the register multiply l, the direct output of the first bit of which is connected to the information input of the first bit of the first buffer register, the output of the It-th element AND the block of the low-order bit is connected to the information input of the (1c + 1) -th bit of the first buffer register, the output of each bit of which is connected to the second inputs of the AND elements of the corresponding row of the matrix, the output of the first element AND of the first row of the matrix is connected to the information input of the first bit of the second buffer register, the output of the -th element OR, group (P t, ..., 2ft-3) connected to; inf by the input (8 +}) - th bit of the second buffer register, the information input (2p -1) of the th digit of which is connected to the output of the n-g element And the i-and row of the matrix, the output of the second buffer register is connected to the inputs of the corresponding bits of the accumulating adder. the output of the nth element AND block of the low-order bit is connected to the first input of the first element AND of the control unit, the second input of which is connected to the synchronization input of the device and the first input of the second element AND of the control block whose second input is connected to the output of the OR element of the control block and output - with the synchronization input of the buffer registers accumulating the adder and the multiplier register, the zero reset input. Which is connected to the information inputs of the corresponding bits of the first buffer register, the output ne The control unit I is connected to the counter input of the control unit, the direct output of the first and the inverse output of the second discharge of which are connected to the inputs of the OR element, the direct output of the second discharge and the overflow output of the second discharge of the counter of the control unit are respectively connected to the control input end-to-end transfer of the accumulating adder and the output of the indication of the end of the operation to multiply the device. FIG. 1 shows a block diagram of the device for the case when FIG. 2 is a functional diagram of the discharge unit; in fig. 3 is a functional block diagram of the control unit; on . FIG. 4 - time diagram of the device. The device contains (Fig. 1) registers 1,2, respectively, multiplier and multiplier, the first buffer register 3, the second buffer register 4, the accumulator adder implemented as a combinational adder 5 and the result register 6 with corresponding links, the matrix of 7 elements And 8, a group of 9 elements OR JO, a block of the allocation of a low-order bit, a control unit 12, a device synchronization input 13 and a device 14 output indication of the end of the multiplication operation. The outputs of the bits of register 1 of the multiplicand are connected to the first inputs of elements AND 8 of the corresponding columns of matrix 7, and the outputs of the bits of the first buffer register 3 are connected to the second inputs of elements AND 8 of the corresponding rows of matrix 7, the output of the j-th element AND O of the 1st row of the matrix 7 rows matri1u 1 (i 1, ..., 4; j 1, ..., 4), except for the first element And 8 of the first row of the matrix 7 and the fourth element And 8 of the fourth row of the matrix 7, is connected to the input (ftj -2 ) -th element OR 10 of group 9, the output of the first element AND 8 of the first row of the matrix 7 is connected to the information input m of the first bit of the second bumper register 4, output of the -th element OR 10 of group 9 (, ..., 5) is connected to the information input of the (+) -th bit of the second buffer register 4, the information input of the seventh bit of which is connected to the output the fourth element AND 8 of the fourth row, the matrix 7, the outputs of the bits of the second buffer register 4 are connected to the inputs of the corresponding bits of the accumulating adder, the forward and inverse outputs of the bits of register 2 multiplier are connected to the inputs of the block 11 of the lower digit whose outputs connected to info The optimal inputs of the corresponding bits of the first buffer register 3 and to the input are wrapped with 1x of the corresponding bits of the register 2 multiplier, the output of the end of the allocation of the selection block 11 for the low-order bit is connected to the first input of the block. 12, the second input of which is connected to the input 13 of the device synchronization, the first output of the control unit 12 is connected to the synchronization inputs of the buffer registers 3 and 4, the accumulating sum of the matrix and the multiplier 2 register, the second output of the control unit 12 is connected to the control input of the end-to-end transfer of the accumulating adder and the third output of the control unit 12 is connected to the output 14 of the indication of the end of the multiplication operation of the device. All device registers can be built on push-pull synchronous JV-flip-flops, with each discharge register register 6 of the accumulating adder using two such flip-flops (one trigger is designed for storing bit sums of the adder 5, and the other for storing its bit-shifting) . Adder 5 is made of combinational type with recording of bit transfers and with the possibility of their end-to-end transmission on the last multiplication stage by applying the appropriate signal to its control input. The low-order allocation block 11 is intended for sequential allocation of units of the g-bit of a binary multiplier code, starting with its low-order bits stored in register 2 of the multiplier. It contains (Fig. 2) P elements and 15 N functions in accordance with the following logical expressions P1, P2. ,, -, i52V4 1 where P, P., P, P. are the signs of the release, respectively the second, third and fourth significant bits of register 2 multiplier; P sign of the end of the allocation of significant bits of the register 2 multiplier; , y - multiply binary numbers--. l y, and the increase of the indices with the letter designations in the direction taken by the iB direction of the higher bits. This version of the construction of the block 11 allocation of the lower bit has an extremely high speed, especially at small values of the size of the information processed in the device. For large values of t, due to the limited capabilities of the logical elements, it is advisable in block 11 to use the principle of dividing it into groups with sequential or parallel transfer between groups of attributes P of the end of the selection of significant bits in groups. This allows even at 56 and the existing elemental base to provide a time for the separation of a significant bit, not exceeding the value of C; where f is the delay of the signal on one logical element. The control unit 12 comprises (FIG. 3) the first element AND 16, the second element AND 17, the element OR 18 and the two-bit binary counter 19 (the counter size may be different), with the first input. control unit 12 is connected to the first input of the first element AND 16, the second input of which is connected to the second input of the control unit 12 and to the first input of the second element AND 17, the second input of which is connected to the clock input of the OR element 18, and the output is the first output of the control unit 12 The output of the first element AND 16 is connected to the input of the counter 19, the direct output of the first and the inverse output of the second bit of which are connected to the inputs of the element OR 18, the direct output of the second bit and the overflow output of the second bit of the counter 12 are respectively second m and the third output unit 12 controls. The device works as follows. 7. Let it be necessary to multiply the n-times multiplier X by an n-bit multiplier 1010. In the initial state, the binary code of the unsigned number X is stored in the register 1 of the multiplicand, in register 2 the multiplier is the binary code of the unsigned U, buffer registers 3.4, the register 6 of the result of the accumulating adder and the counter 19 of the control unit 12 are reset. In the first cycle of operation of the device, at the output of the low-order allocation block 1I, the indication of the selection of the second significant row of register 2 multiplier is formed. The first clock cycle ends when the first sync pulse device arrives at the synchronization input 13, according to which the output of the second element 17 of the control unit 12 is formed by controlling the signal from whose resolution the sign of the second digit of the multiplier register 2 is set to zero and the second digit is written the first buffer register 3. In the second cycle of operation of the device at the output of block 1 1. the selection of the lower bit forms the indication of the allocation of the fourth significant bit of register 2 multiplier, and at the same time under the potential of the logical unit recorded in the second bit of the first buffer register. 3, transfers the corresponding. shifted multiplier from the outputs of the AND 8 elements of the second row of the matrix 7 through the elements OR 10 of group 9 to the information inputs of the second buffer register 4, the clock ends with the arrival at the input .13 of the synchronization of the second sync pulse by which at the output of the second element AND 17 of the control unit 12 a control signal is generated, from which p the information is recorded The second buffer register 4 from its information inputs, as well as on the basis of, sets the fourth bit of the register 2 to the multiplier and records the unit to the fourth bit of the first buffer register 3 (the second bit of the buffer register 3 is updated, since its triggers work how B - triggers). 3 In the third cycle of operation of the device, at the output of the end of the allocation of block I1 of the low-order bit, the feature P - 1 is formed, meaning that the selection of significant bits of register 2 of the multiplier is completed, and at the same time under the action of the potential of the logical unit recorded in the fourth bit of the first the buffer register 3, the corresponding shifted multiplier from the outputs of the AND 8 elements of the fourth row of the matrix 7 is transmitted directly and through the OR elements of group 9 to the information inputs of the second buffer register 4, and, in addition, in the transfer memory accumulator 5, the contents of the second buffer register 4 and the result register 6 (the supported result register 6 is still zero) is summed up, after which the result of the adder 5 in the double-row code arrives at the information inputs of the register 6 result. The third clock cycle ends when the third sync pulse arrives at the synchronization input 13, according to which a signal is generated at the output of the first element AND 16 of the control unit I2, which sets the counter 19 of the control unit 12 to one, and at the output of the second element I) 7 of the control unit 12, a control signal is generated with the permission of which information is recorded in the second buffer register 4 and in the result register 6 from their information inputs. In the fourth cycle of operation of the device in the adder 5, the accumulation of the contents of the second buffer register 4 and the register 6 of the result is summed up, after which the result obtained at its outputs in the two-row code goes to the information inputs of the result register 6. The clock ends with the arrival at the synchronization input 13 of the fourth clock pulse, according to which at the output of the second element AND 17 of the control unit 12 a control signal is formed. with the resolution of which information is recorded in the result register 6 from its information inputs, and at the output of the first element 16 of the control unit 12 a signal is generated that the counter is set through the account input to a state equal to two. According to this counting state, a control signal is generated at the second output of the control unit 12, which further adjusts the adder 5 to work in the end-to-end transfer mode. In the fifth cycle of operation of the device in the adder 5, the possession of the register 6 of the result is summed in the through-transfer mode. The fifth cycle ends with the sync pulse input to the synchronization input 13, according to which only at the output of the first element AND 16 of the control unit 12 a signal is generated that sets the counter 19 through its counting input to the state equal to three. In this cycle, at the output of the second element And 17 of the control unit 12, the control signal is not formed and therefore the information is not recorded in all registers of the device. In the sixth cycle, the process of summation continues with the end-to-end transfer of the contents of register 6 of the result, which was started as early as the beginning of the fifth cycle. Here it is assumed that by the end of the sixth clock cycle, at the outputs of the adder 5, the final result is formed in a one-way code, which arrives accordingly at the information inputs of the result register 6. The sixth clock cycle ends when the sixth sync pulse arrives at the synchronization input 13, at which at the output of the second element 17 of control unit 12 a control signal is generated, the resolution of which records the final result to the result register 6 from its information inputs and at the output of the first element 11 16 of the control unit 12, a signal is generated which, acting through the counting input of the counter 19, resets it to zero and causes the output of the counter 19 of the 1 st signal to indicate that the multiplication in device of the considered numbers. FIG. 4 is a simplified 1 time diagram of the operation of the device when it multiplies the numbers discussed above. On it, through the SI, the sync pulses are input to the synchronization input 13 of the device; signals US1, US2 and HSS correspond to the control signals on the first, second and third outputs of control unit 12, respectively; the sign of the end of the selection, formed in the block 1 of the first low-order gap; C 16 denotes the signal that is formed at the output of the first element AND 16 of the control unit 12 during operation of the device. The average multiplication time of two M-bit numbers in the proposed device, assuming that the appearance of zero and one in all digits of the multiplier is equally likely, is T t 4 + op t where t is the duration of one cycle of the proposed device . The component 4 -t in the above expression is caused by the use of the conveyor principle of information processing in the device, as well as the loss of time for end-to-end transfer of transfers in the adder at the end of the multiplication operation (summation with end-to-end transfer in the adder can be performed during two cycles of operation of the device). Although in the intended device it is necessary to perform four clocks more than two devices of the prototype in multiplying two n-bit binary numbers, but it has a significantly higher speed, since its operation time is minimized (the duration of the operation of the proposed device the time of recording information in registers 2, 3, 4, 6 and the information delaying time is determined either at the block 11 for allocating the least significant bit, or at the matrix 7 of the elements AND 8 and at the elements OR 10 of the group 9, or at the adder 5 Job present in the storage hyphenation mode).

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Claims (1)

DEVICE FOR MULTIPLICATION, * containing registers of the multiplier and multiplier, the matrix of AND elements, the group of OR elements, the accumulating adder and the low-order block, the output of the bits of the register of the multiplier connected to the first inputs of the AND elements of the corresponding matrix columns, the output is j-ro ele-. ment And of the ith row of the matrix (i = 1, ..., ft; j = 1, ..., η; η is the width of the factors), except for the first element And the first row of the matrix and the ith element And the nth matrix rows, connected to the input of the (i + j -2) th element OR group, characterized in that, in order to improve performance, two buffer registers and a control unit containing a counter, two Y elements and an OR element, a block are introduced the low-order selection contains η. elements AND, and the accumulating adder is designed as an adder with storage of transfers, while the inputs of the –th element AND of the block the least significant bit (k = 1, ..., b-1) are connected to the direct output (k + IJ-th bit of the multiplier register and the inverse outputs of all previous bits of the multiplier register, the inputs of the ηth element AND of the low-order selection block are connected to the inverse outputs of all bits of the register of the multiplier, the direct output of the first bit of which is connected to the information input of the first bit of the first buffer register, the output of the kth element AND of the low-order selection block is connected to the information input of the (to + 1) th bit of the first buffer register, each output the discharge of which is connected to the second inputs of the elements AND of the corresponding row of the matrix, the output of the first element AND of the first row of the matrix is connected to the information input of the first bit of the second buffer register, the output of the ith element OR group (¢ = 1, ..., 2n-3) connected to the information input of the (¢ + 1) -th discharge of the second buffer register, the information input of the (2n-1) -th discharge of which is connected to the output of the nth element And the nth row of the matrix, the outputs of the bits of the second buffer register are connected to the inputs corresponding digits of the accumulating sum ator, the output of the ηth element AND of the low-order selection block is connected to the first input of the first element AND of the control unit, the second input of which is connected to the synchronization input of the device and the first input of the second element AND of the control unit, the second input of which is connected to the output of the OR element of the control unit, and the output is with the inputs of the synchronization of the buffer registers, the accumulating adder and the register of the multiplier, the inputs of zeroing the bits of which are connected to the information inputs of the corresponding bits of the first buffer register, the output of the first AND element of the control unit is connected to the input of the counter of the control unit, the direct output of the first and inverse output of the second bits of which are connected to the inputs of the OR element, the direct output of the second category and the overflow output of the second category of the counter of the control unit are connected respectively to the control input of the through transfer of the accumulating adder and output indication end. device multiplication operations.