SU1420600A1 - Function computing device - Google Patents

Abstract

The invention relates to computing and can be used in the construction of digital computers for special and general purposes. The aim of the invention is to simplify the device. The goal is achieved by the fact that in the device containing three registers 2, 6, 9 and adder 5, a trigger 7 is entered, two groups of elements AND 4, 10. As a result, the-. The switching of a number of elements from the prototype device is much simpler. 1 ill., 1 tab.

Description

the group of elements And 4 is connected to the inlet 25 of Y. The trigger 7 goes into the states of the adder 5 of the buffer register 6. The trigger 7 is a regular DJ trigger. Its input S is connected to the input, 3 shifts of the device, the input C of the synchronization is connected to the input 8 of the device, the information input D is connected to the output of the sign bit of the adder 5. The single output of the trigger 7 is connected to the input of the adder 5

1. At the same time, in register 2, the argument X is shifted. In register 6, the previous sum S, -1 from the adder is written with a shift of 2 bits towards the higher bits. Upon completion of the shift at the outputs of the group of elements And 4, a partial square X is formed, at the outputs of the group of elements And 10, a partial square is formed

(n + 4) -th digit), the input of the register 9 ,, square Y, which comes in sum

40

and inputs of the second group of elements AND 10. The result register 9 is a conventional left shift register. The shear control is performed on the input 3 of the device. During the shift, the code and from the trigger 7 is recorded in (n-1) -th register bit 9. The outputs of register 9 through the second group of elements And 10 are connected to the inputs 4, 5, ..., (n + 2) -th bit adder 5. A signal O is continuously received at the zero .c input of device 11. Adder 5 is a normal (2n + 2) -disk parallel parallel combiner. Register 6 is the usual (2n + 2) -disk total amount register. The recording of the sum is controlled by input 3. The outputs of the adder 5 are connected to the inputs of the register 6 with a skew of 2 bits, due to which the sum is shifted by 2 bits to the high bits. Upon completion of the calculations, the required function Y is read from output 12

50

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Matrix 5, where the sum S is formed. Upon completion of the summation, the signal C2 is input to input 8. If the sum Sj is negative, the state of the trigger 7 does not change. If s; 7 / O, the trigger 7 enters the state O and Y 0. After the decay of the transient processes, the cycle is completed. The signal C1 is re-applied, and the next cycle is performed.

It is easy to see that the device is implemented in such a way that equality is maintained

X2 + Y2 - 1 0.

The current bit of the function Y is generated in trigger 7 and from its output goes to output 12 and to register 9. At the end of the n + 1 cycle, a parallel result code can be read from outputs 12, 13.

Primer p. Let X be 0.10011101, then 1 is X 0.1001111110110111 and

Y 1 - X2 0.11001010 0011

(see table).

square Y, which arrive in sum

Matrix 5, where the sum S is formed. Upon completion of the summation, the signal C2 is input to input 8. If the sum Sj is negative, the state of the trigger 7 does not change. If s; 7 / O, the trigger 7 enters the state O and Y 0. After the decay of the transient processes, the cycle is completed. The signal C1 is re-applied, and the next cycle is performed.

It is easy to see that the device is implemented in such a way that equality is maintained

X2 + Y2 - 1 0.

The current bit of the function Y is generated in trigger 7 and from its output goes to output 12 and to register 9. At the end of the n + 1 cycle, a parallel result code can be read from outputs 12, 13.

Primer p. Let X be 0.10011101,: then 1 is X 0.1001111110110111 and

Y 1 - X2 0.11001010 0011

(see table).

51420600 .6

Claims (1)

Claims of the invention tata, the outputs of the elements And the second group are connected to the inputs from the fourth A device for calculating the function of the (n + 2) th bits of the first term, Y1 - X, containing registers of the argument adder, the second term, result, the adder, the buffer of which is connected to the output of the buffer register, two groups of elements And, trig - the register, and the outputs from the third to ger, and the shift inputs of all the (2p + 2) -th digits of the adder are connected to the system and the trigger installation input is connected to the information inputs from the first to the device shift input, tg 2n-th bits of the buffer register, the information input of the register is arguably different so that, on the one connected to the input argument Device for. In order to simplify the device, the outputs from the device, the bits of the register of the first – first (p – 2) –th bits of the result elements and the output of the trigger form AND of the first group are connected to the output outputs of the device, input c s (n + 5) - The gopo (2p + 2) th trigger sync bits is the input term of the adder, the device sync house outputs, the forward (n-1) -th and n-th element bits, and the output of the first most significant bit of the register -, the first group is connected to the argument's information source connected to the first on inputs (2n + 1) and (2n + 2) -th inputs of the The first group, the second series of the buffer register, the corresponding second bit output is registered, the trigger output is connected to the argument pa connected to the second input of the (n + 4) th digit of the first term of the second element And the first group, the first day's day, the first, second, third outputs from the second to the 5th bit, and the (n + .3) -th bit of the first end of the argument register are connected to the 25 summand of the adder connected to - the second inputs of the first and the third house of the logical zero of the device, the output of the nth element And the first group consists of the first The totalizer output is connected, the output of the trigger is connected to the information input of the trigger, is given to the second inputs of the elements, and the second direct outputs of the result register of the group and to the serial input are connected to the first inputs of the elements of the regular input of the result Comrade And the second group.